AD7787 datasheet(5/21 Pages) AD

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AD7787

Data Sheet

Rev. A | Page 4 of 20

Parameter

AD7787B

Unit

Test Conditions/Comments

LOGIC INPUTS

All Inputs Except SCLK1

VINL, Input Low Voltage

0.8

V max

VDD = 5 V.

0.4

V max

VDD = 3 V.

VINH, Input High Voltage

2.0

V min

VDD = 3 V or 5 V.

SCLK Only (Schmitt-Triggered Input)1

VT(+)

1.4/2

V min/V max

VDD = 5 V.

VT(−)

0.8/1.4

V min/V max

VDD = 5 V.

VT(+) − VT(−)

0.3/0.85

V min/V max

VDD = 5 V.

VT(+)

0.9/2

V min/V max

VDD = 3 V.

VT(−)

0.4/1.1

V min/V max

VDD = 3 V.

VT(+) − VT(−)

0.3/0.85

V min/V max

VDD = 3 V.

Input Currents

±1

µA max

VIN = VDD or GND.

Input Capacitance

pF typ

All Digital Inputs.

LOGIC OUTPUTS

VOH, Output High Voltage1

VDD − 0.6

V min

VDD = 3 V, ISOURCE = 100 µA.

VOL, Output Low Voltage1

0.4

V max

VDD = 3 V, ISINK = 100 µA.

VOH, Output High Voltage1

V min

VDD = 5 V, ISOURCE = 200 µA.

VOL, Output Low Voltage1

0.4

V max

VDD = 5 V, ISINK = 1.6 mA.

Floating-State Leakage Current

±1

µA max

Floating-State Output Capacitance

pF typ

Data Output Coding

Offset Binary

POWER REQUIREMENTS5

Power Supply Voltage

VDD − GND

2.5/5.25

V min/max

Power Supply Currents

IDD Current6

µA max

65 µA typ, VDD = 3.6 V, unbuffered mode.

145

µA max

130 µA typ, VDD = 3.6 V, buffered mode.

µA max

73 µA typ, VDD = 5.25 V, unbuffered mode.

160

µA max

145 µA typ, VDD = 5.25 V, buffered mode.

IDD (Power-Down Mode)

µA max

Specification is not production tested but is supported by characterization data at initial product release.

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase.

FS[2:0] are the three bits used in the filter register to select the output word rate.

Digital inputs equal to VDD or GND.

The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14).

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