AD7787 datasheet(15/21 Pages) AD

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AD7787

Data Sheet

Rev. A | Page 14 of 20

ADC CIRCUIT INFORMATION

OVERVIEW

The AD7787 is a low power ADC that incorporates an Σ-Δ

modulator, a buffer, and an on-chip digital filter intended for

the measurement of wide dynamic range, low frequency signals,

such as those in pressure transducers, weigh scales, and

temperature measurement applications.

The part has one differential input and one single-ended input. The

inputs can be operated in buffered or unbuffered mode. Buffering

the input channel means that the part can accommodate significant

source impedances on the analog input .The device requires an

external reference of 2.5 nominal. Figure 12 shows the basic

connections required to operate the part.

IN+

F

0.1

F

IN–

OUT–

POWER

SUPPLY

OUT+

REFIN

SCLK

DIN

VDD

GND

AIN+

AIN–

AIN2

AD7787

MICROCONTROLLER

DOUT/RDY

THERMISTOR

10k



Figure 12. Basic Connection Diagram

The output rate of the AD7787 (fADC) is user programmable

with the settling time equal to 2 × tADC. Normal mode rejection

is the major function of the digital filter. Table 12 lists the

available update rates from the AD7787. Simultaneous 50 Hz

and 60 Hz rejection is optimized when the update rate equals

16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this

update rate (see Figure 6).

NOISE PERFORMANCE

Table 13 shows the output rms noise, rms resolution, and peak-

to-peak resolution (rounded to the nearest 0.5 LSB) for the

different update rates and input ranges for the AD7787. The

numbers given are for the bipolar input range with a reference

of 2.5 V. These numbers are typical and generated with a

differential input voltage of 0 V. The peak-to-peak resolution

figures represent the resolution for which there is no code

flicker within a six-sigma limit. The output noise comes from

two sources. The first is the electrical noise in the semiconductor

devices (device noise) used in the implementation of the

modulator. The second is quantization noise, which is added when

the analog input is converted into the digital domain. The device

noise is at a low level and is independent of frequency. The

quantization noise starts at an even lower level but rises rapidly

with increasing frequency to become the dominant noise source.

Table 13. Typical Peak-to-Peak Resolution

(Effective Resolution) vs. Update Rate

Update Rate

Peak-to-Peak

Resolution

Effective

Resolution

9.5

19.5

13.3

21.5

16.7

21.5

16.6

21.5

18.5

33.3

17.5

100

14.5

120

16.5

REDUCED CURRENT MODES

The AD7787 has a current consumption of 160 μA maximum

when operated with a 5 V power supply, the buffer enabled, and

the clock operating at its maximum speed. The clock frequency

can be divided by a factor of 2, 4, or 8 before being applied to

the modulator and filter, resulting in a reduction in the current

consumption of the AD7787. Bits CDIV1 and CDIV0 in the

filter register are used to enter these low power modes (see

Table 14).

When the internal clock is reduced, the update rate is also

reduced. For example, if the filter bits are set to give an update

rate of 16.6 Hz when the AD7787 is operated in full power

mode, the update rate equals 8.3 Hz in divide-by-2 mode. In the

low power modes, there may be some degradation in the ADC

performance.

Table 14. Low Power Mode Selection

CDIV[1:0]

Clock

Typ Current, Buffered (μA)

Typ Current, Unbuffered (μA)

50 Hz/60 Hz Rejection (dB)

146

1/2

1/4

1/8

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