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AD7992

Rev. 0 | Page 25 of 28

MODES OF OPERATION

When supplies are first applied to the AD7992, the ADC

powers up in sleep mode and normally remains in this

shutdown state while not converting. There are three different

methods of initiating a conversion on the AD7992.

MODE 1—USING THE CONVST PIN

A conversion can be initiated on the AD7992 by pulsing the

CONVST signal. The conversion clock for the part is internally

generated so no external clock is required, except when reading

from or writing to the I2C serial port. On the rising edge of

CONVST, the AD7992 begins to power up (see point A in

Figure 31). The power-up time from shutdown mode for the

AD7992 is approximately 1 µs; the CONVST signal must

remain high for 1 µs for the part to power up fully. CONVST

can be brought low after this time. The falling edge of the

CONVST signal places the track-and-hold into hold mode; a

conversion is also initiated at this point (point B in Figure 31).

When the conversion is complete, approximately 2 µs later, the

part returns to shutdown (point C in Figure 31) and remains

there until the next rising edge of CONVST. The master can

then read the ADC to obtain the conversion result. The address

pointer register must be pointing to the conversion result

If the CONVST pulse does not remain high for more than 1 µs,

the falling edge of CONVST still initiates a conversion, but the

result is invalid because the AD7992 is not fully powered up

when the conversion takes place. To maintain the performance

of the AD7992 in this mode, it is recommended that the I2C bus

is quiet when a conversion is taking place.

The cycle timer register and Command Bits C4 to C1 in the

address pointer register should contain all 0s when operating

the AD7992 in this Mode 1. The CONVST pin should be tied

low for all other modes of operation. Prior to initiating a

conversion in this mode, a write to the configuration register is

needed to select the channel for conversion. To select both input

channels for conversion, set D5 and D4 in the configuration

with each CONVST pulse.

Once the conversion is complete, the master can address the

AD7992 to read the conversion result. If further conversions are

required, the SCL line can be taken high while the CONVST

signal is pulsed; then an additional 18 SCL pulses are required

to read the next conversion result.

SCA

7-BIT ADDRESS

FIRST DATA BYTE (MSBs)

SECOND DATA BYTE (LSBs)

SDA

tPOWER-UP

tCONVERT

CONVST

Figure 31. Mode 1 Operation

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