HT82M99E datasheet(14/45 Pages) HOLTEK

14 / 45 page

HT82M99E

Rev. 1.50

November 19, 2004

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

tomatically after the measurement cycle is completed.

But in the other two modes the TON can only be reset by

instructions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writing a 0 to ET can disable the corre-

sponding interrupt services.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs (a timer/event counter reloading will occur at the

same time). When the timer/event counter (reading

TMR) is read, the clock will be blocked to avoid errors.

As clock blocking may result in a counting error, this

must be taken into consideration by the programmer.

Input/Output Ports

There are 12 bidirectional input/output lines in the

microcontroller, labeled from PA to PB, which are

mapped to the data memory of [12H] and [14H] respec-

tively. All of these I/O ports can be used for input and

output operations. For input operation, these ports are

non-latching, that is, the inputs must be ready at the T2

rising edge of instruction

²MOV A,[m]² (m=12H or 14H).

For output operation, all the data is latched and remains

unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC and PBC)

to control the input/output configuration. With this con-

trol register, CMOS/NMOS/PMOS output or Schmitt

trigger input with or without pull-high/low resistor struc-

tures can be reconfigured dynamically under software

control. To function as an input, the corresponding latch

of the control register must write a

²1². The input source

also depends on the control register. If the control regis-

ter bit is

²1², the input will read the pad state. If the con-

trol register bit is

²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS/NMOS/PMOS configurations can be selected

(NMOS and PMOS are available for PA only). These

control registers are mapped to locations 13H and 15H.

After a chip reset, these input/output lines remain at high

levels or in a floating state (depending on the

pull-high/low options). Each bit of these input/output

latches can be set or cleared by

²SET [m].i² and ²CLR

[m].i

² (m=12H or 14H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

There are pull-high/low (PA only) options available for

I/O lines. Once the pull-high/low option of an I/O line is

selected, the I/O line have pull-high/low resistor. Other-

wise, the pull-high/low resistor is absent. It should be

noted that a non-pull-high/low I/O line operating in input

mode will cause a floating state.

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V D D

P B 2 ~ P B 4 ,

P B 7

P A W a k e - u p O p t i o n

R e a d D a t a R e g i s t e r

C K

C o n t r o l B i t

P H

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P L

P A W a k e - u p

P A 7 / T M R

P o r t O u t p u t

C o n f i g u r a t i o n

Input/Output Ports

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