HAL710 datasheet(5/12 Pages) ETC

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ADVANCE INFORMATION

HAL710

Micronas

2. Functional Description

The HAL 710 is a monolithic integrated circuit with two

independent subblocks consisting each of a Hall plate

and the corresponding comparator. Each subblock

independently switches the comparator output in

response to the magnetic field at the location of the

corresponding sensitive area. If a magnetic field with

flux lines perpendicular to the sensitive area is

present, the biased Hall plate generates a Hall voltage

proportional to this field. The Hall voltage is compared

with the actual threshold level in the comparator. The

subblocks are designed to have closely matched

switching points.

The temperature-dependent bias – common to both

subblocks – increases the supply voltage of the Hall

plates and adjusts the switching points to the decreas-

ing induction of magnets at higher temperatures. If the

magnetic field exceeds the threshold levels, the com-

parator switches to the appropriate state. The built-in

hysteresis prevents oscillations of the outputs.

In order to achieve good matching of the switching

points of both subblocks, the magnetic offset caused

by mechanical stress is compensated for by use of

“switching offset compensation techniques”. Therefore,

an internal oscillator provides a two-phase clock to

both subblocks. For each subblock the Hall voltage is

sampled at the end of the first phase. At the end of the

second phase, both sampled and actual Hall voltages

are averaged and compared with the actual switching

point.

The output of comparator 1 (connected to S1) directly

controls the ‘Count Output’. The outputs of both com-

parators enter the ‘Direction Detection Block’ control-

ling the state of the ‘Direction Output’. The ‘Direction

Output’ is ’high’ if the edge at the output of

comparator 1 precedes that at comparator 2. In the

opposite case, ‘Direction Output’ is ’low’. The previous

state of the ‘Direction Output’ is maintained between

edges of the ‘Count Output’ and in case the edges at

comparator 1 and comparator 2 occur in the same

clock period.

Shunt protection devices clamp voltage peaks at the

output pins and VDD-pin together with external series

resistors. Reverse current is limited at the VDD-pin by

an internal series resistor up to

−15 V. No external

reverse protection diode is needed at the VDD-pin for

reverse voltages ranging from 0 V to

−15 V.

Fig. 2–1: Timing diagram

Idd

Direction

VOH

VOL

Count

VOH

VOL

BS2

BS2on

Clock

1/fosc

Output

BS1

BS1on

Idd

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