AD7666AST datasheet(26/29 Pages) AD

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AD7666

Rev. 0 | Page 25 of 28

External Discontinuous Clock Data Read After

Conversion

Though the maximum throughput cannot be achieved using

this mode, it is the most recommended of the serial slave

modes. Figure 41 shows the detailed timing diagrams of this

method. After a conversion is complete, indicated by BUSY

returning LOW, the conversion’s result can be read while both

CS and RD are LOW. Data is shifted out MSB first with 16 clock

pulses and is valid on the rising and falling edges of the clock.

Among the advantages of this method is the fact that

conversion performance is not degraded because there are no

voltage transients on the digital interface during the conversion

process. Another advantage is the ability to read the data at any

speed up to 40 MHz, which accommodates both the slow digital

host interface and the fastest serial reading.

Finally, in this mode only, the AD7666 provides a daisy-chain

feature using the RDC/SDIN pin for cascading multiple con-

verters together. This feature is useful for reducing component

count and wiring connections when desired, as, for instance, in

isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 43. Simultaneous sampling is possible by using a

common CNVST signal. It should be noted that the RDC/SDIN

input is latched on the opposite edge of SCLK of the one used to

shift out the data on SDOUT. Therefore, the MSB of the

“upstream” converter just follows the LSB of the “downstream”

converter on the next SCLK cycle.

SCLK

SDOUT

RDC/SDIN

BUSY

DATA

OUT

AD7666

(DOWNSTREAM)

BUSY

OUT

SCLK

AD7666

(UPSTREAM)

RDC/SDIN

SDOUT

SCLK IN

CNVST IN

CNVST

CS IN

Figure 43. Two AD7666s in a Daisy-Chain Configuration

External Clock Data Read During Conversion

Figure 42 shows the detailed timing diagrams of this method.

During a conversion, while both CS and RD are LOW, the result

of the previous conversion can be read. The data is shifted out

MSB first with 16 clock pulses, and is valid on both the rising

and falling edges of the clock. The 16 bits must be read before

the current conversion is complete; otherwise, RDERROR is

pulsed HIGH and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain feature

in this mode and the RDC/SDIN input should always be tied

either HIGH or LOW.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 18 MHz is recommended to

ensure that all the bits are read during the first half of the

conversion phase. It is also possible to begin to read data after

conversion and continue to read the last bits after a new

conversion has been initiated. This allows the use of a slower

clock speed like 14 MHz.

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