4

KESTX01

PIN LISTING

Signal

Description

XTAL1

Crystal oscillator

XTAL2

Crystal oscillator

DATA

Input data

TXEN

Transmit enable/stand by

OUT

Power amplifier output/antenna interface

OUTB

Power amplifier output/antenna interface

(complementary output)

LF

Phase detector output

FUNCTION

When the IC is enabled (TXEN high) a phase locked loop

locks the output of the VCO to a multiple of a crystal defined

reference input. The output of the VCO operates at the final

output frequency and is the input to a power amplifier stage.

The power amplifier directly drives the antenna.

Signal

Description

LF1

VCO control input

PWRC

Output power control

VCCPA

Power amplifier positive supply

VEE2

Power amplifier ground

VEE1

PLL ground

VCC

Positive supply

VCOTST

VCO test control input

Phase locked loop

Dividers

A divide by 64 prescaler is present in the PLL feedback

loop. The final output frequency is then Fo = 64xFref.

Phase detector

The phase detector used is a phase frequency detector

(PFD) with a current (charge pump) output. This phase

detector has a triangular characteristic for an input phase error

in the range –2

π <θe < 2π. The charge pump provides an

output current in the range

± 50µA and hence gives a phase

detector gain of (50/2

π ) µA/rad (≈8µA/rad).

The advantage of the PFD over a pure phase detector is

that it is also a frequency discriminator and will always lock the

loop irrespective of the initial frequency offset. The PLL loop

characteristics such as lock–up time, capture range, loop

bandwidth and VCO reference sideband suppression are

controlled by the external loop filter.

For certain applications spurious sidebands at the

reference frequency must be adequately suppressed and a

3rd order loop is recommended.

VCO

To minimize external component cost,s the VCO is fully

integrated. The frequency of the VCO is controlled by the

voltage on pin LF.

Reference crystal oscillator

A single transistor Collpits crystal oscillator provides a

reference clock for the PLL. The oscillator is configured for

parallel resonant operation in the fundamental mode (typical

operating frequency of 3–7MHz). The crystal is connected

between pins XTAL2 and VEE1 with external components as

shown in Figure 6.

Alternatively, a reference clock can be provided by an

external source connected to pin XTAL2 Figure 7.

Output stage (PA)

The input signal at pin DATA produces amplitude shift key

(ASK) modulation of the VCO output. This is achieved by

on–off keying of the bias current in the output power amplifier

stage. The output of the PA is a balanced output (pin OUT and

OUTB) and is current source driven (open collector outputs).

The outputs of which should be D.C. referenced to a positive

The current source outputs can drive a PCB antenna directly

(Figure 6) or if a higher output power is required on limited

supply headroom via a simple impedance transforming net-

work. A balanced output stage is used as it automatically

suppresses the even order harmonics of the fundamental. In

order to obtain the benefits of this output stage it is essential

to use a balanced antenna.

Power up

In the intended application, it is expected that the

transmitter will spend a large proportion of time in ‘‘stand by”

not transmitting data. To maximise battery life it is important

that very little quiescent current is taken in this mode.

The ‘‘stand by mode” is selected by setting pin TXEN low

and similarly the transmitter is enabled by setting TXEN high.

To minimize stand–by current TXEN is used to bias an on–

chip npn transistor connected in a common collector

configuration (Figure 3 below). This transistor is used to

provide the supply to large portions of the IC. Collapsing the

supply when TXEN is set low results in a very low stand by

than 0.2Volts.

From an application standpoint the TXEN pin must be able

to source the bias current for the input transistor and should

also be decoupled if possible to prevent high frequency noise

directly coupling into the IC power supply. The value of the

decoupling capacitors and the drive capability of the TXEN

source will affect power up delay. Since TXEN enables the

PLL it is therefore essential that it is set high prior to any data

transmission and that it remains high during the

transmission.Therefore three different power drain modes are

possible

(i) Stand by (TXEN low, DATA low)

(ii) PLL Mode/Transmit SPACE (TXEN high, DATA low)

(iii) Transmit MARK (TXEN high, DATA high)