MCP6141 datasheet(12/32 Pages) MICROCHIP

12 / 32 page

MCP6141/2/3/4

21668A-page 12

2002 Microchip Technology Inc.

FIGURE 3-5:

Timing Diagram for the CS

function on the MCP6143 op amp.

3.8

Layout Considerations

Good PC board layout techniques will help you achieve

the performance shown in the specifications and typical

performance curves. It will also assist in minimizing

Electro-Magnetic Compatibility (EMC) issues.

3.8.1

SURFACE LEAKAGE

In applications where low input bias current is critical,

PC board surface leakage effects and signal coupling

from trace to trace need to be considered.

Surface leakage is caused by a difference in voltage

between traces, combined with high humidity, dust or

other contamination on the board. Under low humidity

conditions, a typical resistance between nearby traces

is 1012

Ω. A 5V difference would cause 5 pA of current

to flow, which is greater than the input current of the

MCP6141/2/3/4 family at 25°C (1 pA, typ).

The simplest technique to reduce surface leakage is

using a guard ring around sensitive pins (or traces).

The guard ring is biased at the same voltage as the

sensitive pin or trace. Figure 3-6 shows an example of

a typical layout.

FIGURE 3-6:

Example of Guard Ring

layout.

Circuit schematics for different guard ring implementa-

tions are shown in Figure 3-7. Figure 3-7A biases the

guard ring to the input common mode voltage, which is

most effective for non-inverting gains. Figure 3-7B

biases the guard ring to a reference voltage (VREF,

which can be ground), which is useful for inverting

gains and precision photo sensing circuits.

FIGURE 3-7:

Two possible guard ring

connection strategies to reduce surface leakage

effects.

3.8.2

COMPONENT PLACEMENT

In order to help prevent crosstalk:

• Separate digital components from analog compo-

nents, and low speed devices from high speed

devices.

• Keep sensitive traces short and straight. Separate

them from interfering components and traces.

This is especially important for high frequency

(low rise time) signals.

• Use a 0.1 µF supply bypass capacitor within 0.1”

(2.5 mm) of the VDD pin. It must connect directly

to the ground plane.

VIL

Hi-Z

tON

VIH

tOFF

VOUT

IVDD

20 pA, typ

Hi-Z

IVSS

ICS

5 pA, typ

5pA, typ

20 pA, typ

0.6 µA, typ

5 pA, typ

0.6 µA, typ

5pA, typ

Guard Ring

VSS

IN-

IN+

VREF

MCP614X

Figure 3-7A

Figure 3-7B

VDD

VREF

MCP614X

VDD

MCP6141 Datasheet(PDF) 12 Page - Microchip Technology

MCP6141 Datasheet(HTML) 12 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL