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ACE24LA64AFMTH Datasheet(PDF) 8 Page - ACE Technology Co., LTD. |
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ACE24LA64AFMTH Datasheet(HTML) 8 Page - ACE Technology Co., LTD. |
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8 / 18 page ![]() ACE24LA64A Two-wire Serial EEPROM VER 1.1 8 Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 9). Read Identification Page: The Identification Page (32 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B15/B6 are don't care, the LSB address bits B5/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes) Lock Identification Page: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: Device type identifier = 1011b Address bit B10 must be „1‟; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care B15 B14 B13 B12 B11 B10 B9 B8 Table 2.First Word Address B7 B6 B5 B4 B3 B2 B1 B0 Table 3.Second Word Address Figure 4: Device Address |
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