ST72F324J datasheet(6/156 Pages) STMICROELECTRONICS

6 / 156 page

ST72324J/K

6/156

1 INTRODUCTION

The ST72324K and ST72324J devices are mem-

bers of the ST7 microcontroller family. They can

be grouped as follows:

– The 32-pin ST72324K devices are designed for

mid-range applications

– The 42/44-pin ST72324J devices target the

same range of applications requiring more than

24 I/O ports.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-

gram memory.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or stand-by state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication

and indirect addressing

modes.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

OSC1

VPP

CONTROL

PROGRAM

(8K - 60K Bytes)

VDD

RESET

PORT F

PF7:6,4,2:0

TIMER A

BEEP

PORT A

RAM

(384 - 2048 Bytes)

PORT C

10-BIT ADC

VAREF

VSSA

PORT B

PB4:0

PORT E

PE1:0

(2 bits)

SCI

TIMER B

PA7:3

(5 bits on J devices)

PORT D

PD5:0

SPI

PC7:0

(8 bits)

VSS

WATCHDOG

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

(4 bits on K devices)

(5 bits on J devices)

(3 bits on K devices)

(6 bits on J devices)

(2 bits on K devices)

(6 bits on J devices)

(5 bits on K devices)

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