PEF80902 datasheet(22/83 Pages) INFINEON

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PEF 80902

Functional Description

Data Sheet

2001-11-12

2.2

IOM-2 Interface

The IOMâ-2 interface always operates in NT mode according to the IOMâ-2 Reference

Guide [12].

2.2.1

IOMâ-2 Functional Description

The IOMâ-2 interface consists of four lines: FSC, DCL, DD, DU. The rising edge of FSC

indicates the start of an IOMâ-2 frame. The DCL clock signal synchronizes the data

transfer on both data lines DU and DD. The DCL is twice the bit rate. The bits are shifted

out with the rising edge of the first DCL clock cycle.

Note: It is not possible to write any data via IOMâ-2 into the T-SMINTâO.

The IOMâ-2 interface can be enabled/disabled with pin DIO.

The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the

transmit line is determined by the frequency of the DCL clock , with the 512 kHz clock 1

channel consisting of 4 timeslots is available.

IOM

®-2 Frame Structure of the T-SMINTâO

The frame structure on the IOMâ-2 data ports (DU,DD) of the T-SMINTâO with a DCL

clock of 512 kHz is shown in Figure 4.

•

Figure 4

IOM-2 Frame Structure of the T-SMINTâO

The frame is composed of one channel:

• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR

programming channel (not available in T-SMINTâO) and a command/indication

channel (CI0) for control of e.g. the U-transceiver.

macro_19_QSMINTO

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