7

ATL25SeriesASIC

1414C–ASIC-08/02

32-bit RISC

Microprocessor

Core

The ARM7TDMI is a powerful 32-bit processor offered as a hard macro core in the ATL25

family.

The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general pur-

pose 32-bit microprocessors, which offer high performance with very low power consumption.

Additionally, the ARM7T offers users a “thumb” mode (for higher code density using 16-bit

instructions

The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and

the instruction set and related decode mechanism are much simpler than those of micropro-

grammed Complex Instruction Set Computers (CISC). This simplicity results in a high

instruction throughput and an impressive real-time interrupt response from a small and cost-

effective chip.

Pipelining is employed so that all parts of the processing and memory systems can operate

continuously. Typically, while one instruction is being executed, its successor is being

decoded, and a third instruction is being fetched from memory.

The ARM memory interface has been designed to allow the performance potential to be real-

ized without incurring high costs in the memory system. Speed-critical control signals are

pipelined to allow system control functions to be implemented in standard low-power logic,

and these control signals facilitate the exploitation of the fast local access modes offered by

industry standard SRAMs.

The ARM7TDMI core interfaces to several optional peripheral macros. Among the peripheral

options offered are real-time clock, peripheral data controller, USART, external bus interface,

interrupt controller, timer counter and watchdog timer.

Figure 4. ARM7TDMI 32-bit RISC Microprocessor Core

Address

Incrementor

Register Bank

(31 X 32-bit Registers)

(6 Status Registers)