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ATL25/352 Datasheet(PDF) 4 Page - ATMEL Corporation |
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ATL25/352 Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 14 page  4 ATL25SeriesASIC 1414C–ASIC-08/02 Table 3. Design Flow Final Design Review Place and Route/ Clock Tree Verification/ Resimulation Define Underlayer Fabricate Underlayer Create Underlayer Tape Out Underlayer Scan/JTAG Floorplan Simulation/ Static Path Synthesis/ Design Entry Deliver Design Kit Kickoff Meeting Atmel Joint Database Handoff If Embedded Array Customer Database Acceptance If Embedded Array (Preliminary Netlist) Fabricate Personality Tape Out Metal Masks Proto Assembly and Test Rev. 2.2-03/02 Fabricate Tape Out Full Mask Set If Embedded/Gate Array If Standard Cell Proto Shipment |
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