5

ATL25SeriesASIC

1414C–ASIC-08/02

Pin Definition

Requirements

The corner pads are reserved for power and ground only. All other pads are fully programma-

ble as input, output, bidirectional, power, or ground. When implementing a design with 3.3V

which are used to distribute 3.3V power to the compliant buffers.

Design Options

Logic Synthesis

Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synop-

sys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and

VHDL, Atmel’s preferred HDL format for ASIC design is Verilog.

ASIC Design

Translation

Atmel has successfully translated existing designs from most major ASIC vendors into Atmel

ASICs. These designs have been optimized for speed and gate count and modified to add

logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement.

FPGA and PLD

Conversions

Atmel has successfully translated existing FPGA/PLD designs from most major vendors into

Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC:

•

Conversion of high-volume devices for a single or combined design is cost effective.

•

Performance can often be optimized for speed or low power consumption.

•

Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing

on-board space requirements.

•

In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may

provide a lower cost answer for long-term volume production.