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CY29773AI Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY29773AI
Description  2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
PDF  12 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29773AI Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY29773
Document #: 38-07573 Rev. **
Page 6 of 12
IIH
Input Current, High[6]
VIL = VDD
–
–
100
µA
IDDA
PLL Supply Current
AVDD only
–
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
–
–
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
–
225
–
mA
CIN
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
12
15
18
Ω
AC Electrical Specifications (VDD = 2.5V ±5%, TA = –40°C to +85°C)
[7]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fVCO
VCO Frequency
200
–
380
MHz
fin
Input Frequency
÷4 Feedback
50
–
95
MHz
÷6 Feedback
33.3
–
63.3
÷8 Feedback
25
–
47.5
÷10 Feedback
20
–
38
÷12 Feedback
16.6
–
31.6
÷16 Feedback
12.5
–
23.75
÷20 Feedback
10
–
19
÷24 Feedback
8.3
–
15.8
÷32 Feedback
6.25
–
11.8
÷40 Feedback
5
–
9.5
Bypass mode (PLL_EN = 0)
0
–
200
frefDC
Input Duty Cycle
25
–
75
%
VPP
Peak-Peak Input Voltage
LVPECL
500
–
1000
mV
VCMR
Common Mode Range[8]
LVPECL
1.2
–
VDD – 0.6
V
tr , tf
TCLK Input Rise/FallTime
0.7V to 1.7V
–
–
1.0
ns
fMAX
Maximum Output Frequency
÷2 Output
100
–
190
MHz
÷4 Output
50
–
95
÷6 Output
33.3
–
63.3
÷8 Output
25
–
47.5
÷10 Output
20
–
38
÷12 Output
16.6
–
31.6
÷16 Output
12.5
–
23.75
÷20 Output
10
–
19
÷24 Output
8.3
–
15.8
fSCLK
Serial Clock Frequency
–
–
20
MHz
DC
Output Duty Cycle
fMAX < 100 MHz
47.5
–
52.5
%
fMAX > 100 MHz
45
–
55
tr , tf
Output Rise/Fall times
0.6V to 1.8V
0.1
–
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
TCLK to FB_IN
–125
–
125
ps
PCLK to FB_IN
–125
–
125
Notes:
7.
AC characteristics apply for parallel output termination of 50
Ω to V
TT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
8.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing
lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit



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