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CY29773
Document #: 38-07573 Rev. **
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D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
Figure 2.
Pulse
G enerator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
RT = 50 ohm
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 4. PECL_CLK AC Test Reference for VDD = 3.3V/2.5V
t(
φ)
PECL_CLK
PECL_CLK
VPP
FB_IN
VCMR
VDD
GND
VDD/2
Figure 5. LVPECL Propagation Delay t(
φ), Static Phase Offset
t(
φ)
LVCMOS_CLK
FB_IN
VDD
GND
VDD/2
VDD
GND
VDD/2
Figure 6. LVCMOS Propagation Delay t(
φ), Static Phase Offset
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