CY29773AI datasheet(8/12 Pages) CYPRESS

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CY29773

Document #: 38-07573 Rev. **

Page 8 of 12

SYNC Output

In situations where output frequency relationships are not

integer multiples of each other the SYNC output provides a

signal for system synchronization. The CY29773 monitors the

relationship between the QA and the QC output clocks. It

provides a low going pulse, one period in duration, one period

prior to the coincident rising edges of the QA and QC outputs.

The duration and the placement of the pulse depend on the

higher of the QA and QC output frequencies. The following

timing diagram illustrates various waveforms for the SYNC

output. Note that the SYNC output is defined for all possible

combinations of the QA and QC outputs even though under

some relationships the lower frequency clock could be used

as a synchronizing signal.

fMAX

Maximum Output Frequency

÷2 Output

100

–

200

MHz

÷4 Output

–

125

÷6 Output

33.3

–

83.3

÷8 Output

–

62.5

fMAX

Maximum Output Frequency

(continued)

÷10 Output

–

MHz

÷12 Output

16.6

–

41.6

÷16 Output

12.5

–

31.25

÷20 Output

–

÷24 Output

8.3

–

20.8

fSCLK

Serial Clock Frequency

–

MHz

Output Duty Cycle

fMAX < 100 MHz

–

fMAX > 100 MHz

–

tr , tf

Output Rise/Fall times

0.55V to 2.4V

0.1

–

1.0

t(φ)

Propagation Delay (static phase

offset)

TCLK to FB_IN, same VDD

–125

–

125

PCLK to FB_IN, same VDD

–125

–

125

tsk(O)

Output-to-Output Skew

Skew within Bank A

–

Skew within Bank B

–

100

Skew within Bank C

–

150

tsk(B)

Bank-to-Bank Skew

–

325

tPLZ, HZ

Output Disable Time

–

tPZL, ZH

Output Enable Time

–

PLL Closed Loop Bandwidth

(–3 dB)

÷4 Feedback

–

1.3–2.0

–

MHz

÷6 Feedback

–

0.7–1.3

–

÷8 Feedback

–

0.9–1.3

–

÷10 Feedback

–

0.6–1.1

–

÷12 Feedback

–

0.6–0.9

–

÷16 Feedback

–

0.4–0.6

–

÷20 Feedback

–

0.6–0.9

–

tJIT(CC)

Cycle-to-Cycle Jitter

Same frequency (125 MHz)

RMS (1

σ)

–

Same frequency

–

100

Multiple frequencies

–

375

tJIT(PER)

Period Jitter

Same frequency (125 MHz)

RMS (1

σ)

–

Same frequency

––

Multiple frequencies

–

225

tJIT(φ)

I/O Phase Jitter

I/O same VDD

––

150

tLOCK

Maximum PLL Lock Time

–

AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)

[7]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

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