ADATE318BCPZ datasheet(51/81 Pages) AD

51 / 81 page

ADATE318

Data Sheet

Rev. B | Page 50 of 80

USE OF THE SPI BUSY PIN

After any valid SPI instruction is written to the ADATE318, the

BUSY pin becomes asserted to indicate a busy status of the DAC

update and calibration engines. The BUSY pin is an open drain

type output capable of sinking a minimum of 5 mA from the

VCC supply. Because it is an open drain type output, it can be

wire-or’ed in common with many other similar open drain

devices. In such cases, it is the user’s responsibility either to

determine which device is indicating the busy state or, alter-

natively, to wait until all devices on the shared line become not

busy. It is recommended that the BUSY pin be tied to VCC with

an external 1 kΩ pull-up.

It is not a requirement to wait for release of BUSY prior to a

subsequent assertion of the CS pin. This is not the purpose of

the BUSY pin. As long as the minimum number of SCLK cycles

following the previous release of CS is met according to the

tCSAM parameter, the CS pin can be asserted again for a

subsequent SPI operation. With the one exception of recovery

from a reset request (either by hardware assertion of the RST

pin or a sofware setting of the internal SPI_RESET control bit),

there is no scenario in normal operation of the ADATE318 in

which the user must wait for release of BUSY prior to asserting

the CS for another SPI operation. The only requirement on the

assertion of CS is that the tCSAM parameter be defined as in

Figure 4 and Table 13.

It is very important, however, that the SCLK continue to operate

for as long as the BUSY pin state remains active. This minimum

period of time is defined by the tBUSW parameter (see Figure 4,

Figure 6, Figure 7, and Table 18). If the SCLK does not remain

active for at least the time specified by the tBUSW parameter, oper-

ations pending to the internal processor may not fully complete

or, worse, they may complete in an incorrect fashion. In either

case, a temporary malfunction of the ADATE318 may occur.

After the ADATE318 releases the BUSY pin, the SCLK may

again be stopped to prevent unwanted digital noise from

coupling into the analog levels during normal operation of the

pin electronics functions. In every case (with no exception for

reset recovery), it is the purpose of the BUSY pin to notify the

external test processor that it is again safe to stop the SCLK

signal to the ADATE318. Running the SCLK for extra periods

when BUSY is not active is never a problem except for the

possibility of adding unwanted digital switching noise to the

analog pin electronics circuitry as already noted.

While the length of the BUSY period (tBUSW) is variable depending

on the particular preceding SPI instruction, it is nevertheless

deterministic. The parameter tBUSW depends only on factors

such as whether the previous instruction involved a write to one

or more DAC addresses and, if so, then how many channels

were involved and whether or not the calibration function was

enabled. Table 18 describes the precise length of the tBUSW period

in units of rising edge SCLK cycles for each possible SPI

instruction scenario as well as recovery from a hard RST reset.

Because tBUSW is deterministic, it is therefore possible to predict

in advance the minimum number of rising edge SCLK cycles

required to complete any given SPI instruction. This makes it

possible to operate the ADATE318 without a need to monitor

the state of the BUSY pin. For applications in which it is neither

possible nor desireable to monitor the pin, it is acceptable to use

the information in Table 18 to guarantee that the minimum

number of cycles is provided in lieu of monitoring BUSY

following release of CS or reset. All DAC addresses have been

assigned to the contiguous address block from 0x00 through

0x0F; therefore, it is possible to decode this information within

the external test processor to provide a software indication that

extra SCLK cycles may be required according to the scenarios

listed in Table 18. All other operations not involving these

addresses require only the standard number of clock cycles

determined by tCSAM. As stated above, however, it is extremely

important to honor the minimum number of required rising

edge SCLK cycles as defined by tBUSW following the release of CS

for each of the SPI instruction scenarios listed in Table 18 to

ensure proper operation of the ADATE318.

Table 18. BUSY Minimum SCLK Cycle Requirements

SPI Instruction Type

Calibration Engine1

Maximum tBUSW (SCLK Cycles)

Following the Release of the Asynchronous Reset Pin (Hardware Reset)

Following Assertion of the SPI_RESET Control Bit (Software Reset)

No Operation (NOP) Instruction

Read Request to Any Valid ADATE318 Address and/or Channel (0x00 – 0x7F)

Single/Double Channel Write Request to Any Valid ADATE318 Address ≥ 0x10

Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)

Disabled

Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)

Disabled

Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)

Enabled

Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E)

Enabled

X = don’t care.

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