ADATE318BCPZ datasheet(25/81 Pages) AD

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ADATE318

Data Sheet

Rev. B | Page 24 of 80

SCLK

SDI

SPI RESET

BUSY

DAC0

DAC1

DAC23

PREVIOUS CODE

DEFAULT DAC0 CODE

VDUTGND

PREVIOUS CODE

DEFAULT DAC1 CODE

VDUTGND

PREVIOUS CODE

DEFAULT DAC23 CODE

INITIALIZED

CONDITION

RESET

CONDITION

VDUTGND

tCH

tCL

tBUSA

tBUSR

tBUSW

SEE TABLE 18

3µs

(DAC DEGLITCH)

Figure 5. SPI Detailed Software Reset Timing Diagram

SCLK

SDI

SDO

BUSY

FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18)

CH[1:0]

ADDR[6:0]

DATA[15:0] = DON’T CARE

NOTE 1

ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI

NOTES

1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION

OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN ALWAYS

REMAINS ACTIVE INDEPENDENT OF CS.

Figure 6. SPI Read Request Instruction (Prior to Readout)

ADATE318BCPZ Datasheet(PDF) 25 Page - Analog Devices

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