CX28331 datasheet(44/68 Pages) CONEXANT

44 / 68 page

2.0 Functional Description

CX28331/CX28332/CX28333

2.3 Receiver

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2-12

Conexant

100985A

When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs

are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then

decoded by the Framer or other downstream device. Line code violations are not

detected in this mode of operation. The decoder is configurable for either:

•

E3 mode using HDB3 coding (E3MODE = 1)

•

DS3/STS-1 mode using B3ZS coding (E3MODE = 0)

The receiver digital data outputs are centered on the rising edge of RCLK

(see Section 2.9).

2.3.7 Data Squelching

A counter in the receiver keeps track of the number of consecutive symbol

periods without a valid data pulse. When 128 or more 0s in a row are counted, the

receiver assumes that it has lost the signal and resets itself to try and regain the

signal. While the receiver is reacquiring the signal, the clock recovery block locks

to the reference clock and the data squelching is achieved by forcing the data bits

to zero. The data squelching is true in both NRZ and dual rail mode. When the

input signal has been properly amplified and equalized, the clock recovery PLL

will then switch to the incoming data.

CX28331 Datasheet(PDF) 44 Page - Synaptics Incorporated.