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AD9874EB Datasheet(PDF) 1 Page - Analog Devices |
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AD9874EB Datasheet(HTML) 1 Page - Analog Devices |
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1 / 40 page  REV. 0 a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD9874* IF Digitizing Subsystem *Protected by U.S. Patent No. 5,969,657; other patents pending. FEATURES 10 MHz–300 MHz Input Frequency 6.8 kHz–270 kHz Output Signal Bandwidth 8.1 dB SSB NF 0 dBm IIP3 AGC Free Range up to –34 dBm 12 dB Continuous AGC Range 16 dB Front End Attenuator Baseband I/Q 16-bit (or 24-bit) Serial Digital Output LO and Sampling Clock Synthesizers Programmable Decimation Factor, Output Format, AGC, and Synthesizer Settings 370 Input Impedance 2.7 V–3.6 V Supply Voltage Low Current Consumption: 20 mA 48–Lead LQFP Package (1.4 mm Thick) APPLICATIONS Multimode Narrowband Radio Products Analog/Digital UHF/VHF FDMA Receivers TETRA, APCO25, GSM/EDGE Portable and Mobile Radio Products Base Station Applications GENERAL DESCRIPTION The AD9874 is a general-purpose IF subsystem that digitizes a low level 10 MHz–300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874 consists of a low noise amplifier, a mixer, a band-pass sigma-delta analog-to-digital converter, and a decimation filter with program- mable decimation factor. An automatic gain control (AGC) circuit gives the AD9874 12 dB of continuous gain adjustment. Auxiliary blocks include both clock and LO synthesizers. The AD9874’s high dynamic range and inherent antialiasing provided by the band-pass sigma-delta converter allow the AD9874 to cope with blocking signals up to 95 dB stronger than the desired signal. This attribute can often reduce the cost of a radio by reducing its IF filtering requirements. Also, it enables multimode radios of varying channel bandwidths, allowing the IF filter to be specified for the largest channel bandwidth. The SPI port programs numerous parameters of the AD9874, thus allowing the device to be optimized for any given application. Programmable parameters include the following: synthesizer divide ratios; AGC attenuation and attack/decay time; the received signal strength level; decimation factor; the output data format; 16 dB attenuator; and the selected bias currents. The bias currents of the LNA and mixer can be further reduced at the expense of the degraded performance for battery- powered applications. FUNCTIONAL BLOCK DIAGRAM - ADC LNA DAC AGC VOLTAGE REFERENCE SPI CONTROL LOGIC FORMATTING/SSI DECIMATION FILTER LO SYNC SAMPLE CLOCK SYNTHESIZER LO VCO AND LOOP FILTER IFIN FREF DOUTA DOUTB FS CLKOUT SYNCB PE PD PC VREFN VCM VREFP MXOP MXON IF2P IF2N GCP GCN –16dB AD9874 CLKN CLKP IOUTC LON LOP IOUTL LO VCO AND LOOP FILTER |
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