AD9874EB datasheet(20/40 Pages) AD

20 / 40 page

REV. 0

–20–

AD9874

The bias, IBIAS, of the negative-resistance core has four pro-

grammable settings. Lower equivalent Q of the LC tank circuit

may require a higher bias setting of the negative-resistance core

to ensure proper oscillation. RBIAS should be selected so the

common-mode voltage at CLKP and CLKN is approximately

1.6 V. The synthesizer may be disabled via the CK standby bit

to allow the user to employ an external synthesizer and/or VCO

in place of those resident on the IC. Note, if an external CLK

source or VCO is used, the clock oscillator must be disabled via

the CKO standby bit.

The phase noise performance of the clock synthesizer is depen-

dent on several factors, including the CLK oscillator IBIAS

setting, the charge pump setting, the loop filter component

values, and the internal fREF setting. Figures 7b and 7c show

how the measured phase noise attributed to the clock synthe-

sizer varies (relative to an external fCLK) as a function of the

IBIAS setting and charge pump setting for a –31 dBm IFIN signal

at 73.35 MHz with an external LO signal at 71.1 MHz. Figure

7b shows that the optimum phase noise is achieved with the

highest IBIAS (CKO) setting, while Figure 7c shows that the

higher charge pump values provide the optimum performance

for the given loop filter configuration. The AD9874 clock syn-

thesizer and oscillator were set up to provide a fCLK of 18 MHz

from an external fREF of 16.8 MHz. The following external

component values were selected for the synthesizer: RF = 390

Ω,

RD = 2 k

Ω, C

Z = 0.68

µF, C

P = 0.1

µF, C

OSC = 91 pF, LOSC =

1.2

µH, and CVAR = Toshiba 1SV228 Varactor.

–25

–90

–100

–110

–120

–20

–15

–10

–5

CKO = 0

FREQUENCY OFFSET – kHz

–80

–70

–60

–50

–40

–30

–20

–10

CKO = 1

CKO = 2

EXT CLK

Figure 7b. CLK Phase Noise vs. IBIAS Setting (CKO)

(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60

with fREF = 100kHz)

CLOCK SYNTHESIZER

The clock synthesizer is a fully programmable integer-N PLL

capable of 2.2 kHz resolution at clock input frequencies up to

18 MHz and reference frequencies up to 25 MHz. It is similar

to the LO synthesizer described previously in Figure 4 with the

following exceptions:

•

It does not include an 8/9 prescaler nor an A counter.

•

It includes a negative-resistance core that when used in conjunc-

tion with an external LC tank and varactor, serves as the VCO.

The 14-bit reference counter and 13-bit N-divider counter can

be programmed via the following registers: CKR and CKN.

The clock frequency, fCLK, is related to the reference

frequency by the following equation:

CKN CKR

CLK

REF

() ×

(5)

The charge pump current is programmable via the CKI register

from 0.625 mA to 5.0 mA using the following equation:

CKI

PUMP

() ×

10 625

(6)

The fast acquire subcircuit of the charge pump is controlled by

the CKFA Register in the same manner as the LO synthesizer is

controlled by the LOFA Register. An on-chip lock detect function

(enabled by the CKF bit) automatically increases the output

current for faster settling during channel changes. The synthe-

sizer may also be disabled using the CK standby bit located in

the STBY Register.

CLK OSC. BIAS

IBIAS = 0.15 mA, 0.25 mA,

0.40 mA, OR 0.65 mA

VDDC = 3.0 V

IOUTC

LOSC

0.1 F

RBIAS

COSC

LOOP

FILTER

CVAR

AD9874

CLKN

CLKP

VCM = VDDC – RBIAS

IBIAS > 1.6V

OSC > 1/{2

(LOSC (CVARACTOR//COSC))1/2}

Figure 7a. External Loop Filter, Varactor, and LC Tank

Are Required to Realize a Complete Clock Synthesizer

The AD9874 clock synthesizer circuitry includes a negative-

resistance core so that only an external LC tank circuit with a

varactor is needed to realize a voltage controlled clock oscillator

(VCO). Figure 7a shows the external components required to

complete the clock synthesizer along with the equivalent input

circuitry of the CLK input. The resonant frequency of the VCO

is approximately determined by LOSC and the series equivalent

capacitance of COSC and CVAR. As a result, LOSC, COSC, and

CVAR should be selected to provide a sufficient tuning range to

ensure proper locking of the clock synthesizer.

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