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ADUCM310 Datasheet(PDF) 15 Page - Analog Devices |
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ADUCM310 Datasheet(HTML) 15 Page - Analog Devices |
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15 / 28 page  ADuCM310 Data Sheet Rev. B Page 14 of 27 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit tSL SCLKx low pulse width (SPIxDIV1 + 1) × tHCLK2/2 ns tSH SCLKx high pulse width (SPIxDIV1 + 1) × tHCLK2/2 ns tDAV Data output valid after SCLKx edge 0 3 ns tDOSU Data output setup before SCLKx edge ½ SCLKx ns tDSU Data input setup time before SCLKx edge SCLKx ns tDHD Data input hold time after SCLKx edge SCLKx ns tDF Data output fall time 25 ns tDR Data output rise time 25 ns tSR SCLKx rise time 20 ns tSF SCLKx fall time 20 ns 1 For SPI0, x is 0, and for SPI1, x is 1. 2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0]. SCLKx (POLARITY = 0) SCLKx (POLARITY = 1) tSH tSL tSR tSF MOSIx MSB BIT 6 TO BIT 1 LSB MISOx MSB IN BIT 6 TO BIT 1 LSB IN tDR tDF tDAV tDOSU tDSU tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) |
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