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ADUCM310 Datasheet(PDF) 16 Page - Analog Devices |
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ADUCM310 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 28 page  Data Sheet ADuCM310 Rev. B Page 15 of 27 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit tCS0/tCS1 CS0/CS1 to SCLKx edge 10 ns tCSM CS0/CS1 high time between active periods SCLKx ns tSL SCLKx low pulse width (SPIxDIV1 + 1) × tHCLK2 ns tSH SCLKx high pulse width (SPIxDIV1 + 1) × tHCLK2 ns tDAV Data output valid after SCLKx edge 20 ns tDSU Data input setup time before SCLKx edge 10 ns tDHD Data input hold time after SCLKx edge 10 ns tDF Data output fall time 25 ns tDR Data output rise time 25 ns tSR SCLKx rise time 1 ns tSF SCLKx fall time 1 ns tSFS CS0/CS1 high after SCLKx edge 20 ns 1 For SPI0, x is 0, and for SPI1, x is 1. 2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0]. SCLKx (POLARITY = 0) CS0/CS1 SCLKx (POLARITY = 1) tSH tSL tSR tSF tSFS MISOx MSB BIT 6 TO BIT 1 LSB MOSIx MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU tDAV tDR tDF tCS0/tCS1 tCSM Figure 5. SPI Slave Mode Timing (Phase Mode = 1) |
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