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ATPL230A Datasheet(PDF) 120 Page - ATMEL Corporation |
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ATPL230A Datasheet(HTML) 120 Page - ATMEL Corporation |
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120 / 122 page  ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 120 D Minor changes. Signal Description CLKOUT: “20 MHz CLK Output” changed to “10 MHz External Clock Output”. SPI Controller Chapter added. MAC Coprocessor “Address: 0xFE62 - 0xFE67” changed to “Address: 0xFEBA (MSB) - 0xFEBB (LSB)” in Section 8.3.1.2 ”CRC32 Errors Counter Register”. PRIME PHY Layer “Reset: 0x000000” changed to “Reset: 0x00000000” in Section 9.3.3.9 ”Accumulated Header EVM Registers”. “Reset: 0x000000” changed to “Reset: 0x00000000” in Section 9.3.3.10 ”Accumulated Payload EVM Registers”. “Reset: 0x00000000” changed to “Reset: 0x000124F8” in Section 9.3.5.4 ”TX Timeout Registers”. “Reset: 0x0000” changed to “Reset: 0x1111” in Section 9.3.5.7 ”TX Result Register”. C “GND” changed to “AGND” in the following pins: 62, 67, 72 and 73. Changed the description of “VDDIN AN” in Section 3. ”Signal Description”. B Update Package. A First Issue. Doc Rev. 43053 Comments Change Request Ref. |
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