VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC7126

1.0625 Gbits/sec Fibre

Channel Transceiver

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

3/4/99

G52148-0, Rev. 4.3

Functional Description

Clock Synthesizer:

The VSC7126 clock synthesizer multiplies the 53.125 MHz reference frequency provided on the TBC pin

by 20 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic

PLL which does not require any external components.

Serializer:

The VSC7126 accepts TTL input data as two parallel 10 bit characters on the T0:19 bus which is latched

into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL dif-

ferential outputs at a baud rate of twenty times the frequency of the TBC input, with bit T0 transmitted first.

User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel spec-

ification, or an equivalent, edge rich, DC-balanced code. If either EWRAP or TXEN# is HIGH the transmitter

will be disabled with TX+ HIGH and TX- LOW. If both EWRAP and TXEN# are LOW, the transmitter outputs

serialized data.

Transmission Character Interface

In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20 bit inter-

face on the VSC7126 corresponds to two transmission characters. This mapping is illustrated in Figure 1.

Figure 1: Transmission Order and Mapping to Fibre Channel Character

Clock Recovery:

The VSC7126 accepts differential high speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW),

extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and lim-

ited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7126 clock recovery

circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of

the data stream to be recovered should be within 200 ppm of twenty times the TBC frequency. This allows

oscillators on either end of the link to be 53.125 MHz +/- 100ppm.

Deserializer:

The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7126 provides

a TTL recovered clock, RBC(0) and its complement RBC(1), at one-twentieth of the serial baud rate. The

clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial

data is retimed by the internal high-speed clock, and deserialized. The resulting parallel data will be captured

Parallel Data Bits

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

0

8B/10B Bit Position

j

hgf

i

e

dc

ba

j

hgf

i

e

dc

ba

Valid Comma Position

1111100

First Data Bit Transmitted

Last Data Bit Transmitted