PC755 datasheet(24/50 Pages) ATMEL

24 / 50 page

PC755/745

2138D–HIREL–06/03

Electrical

Characteristics

Static Characteristics

Notes:

1. Nominal voltages; See

Table 5 for recommended operating conditions.

2. For processor bus signals, the reference is OV

DD while L2OVDD is the reference for the L2 bus signals.

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV

DD and VDD, or both OVDD and VDD must vary in the same direction (for example,

both OV

DD and VDD vary by either +5% or -5%).

Dynamic Characteristics

After fabrication, parts are sorted by maximum processor core frequency as shown in

the “Clock AC Specifications” Section on page 25 and tested for conformance to the AC

specifications for that frequency. These specifications are for 275, 300, 333 MHz pro-

cessor core frequencies. The processor core frequency is determined by the bus

(SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by

maximum processor core frequency.

Table 11. DC Electrical Specifications at Recommended Operating Conditions (see Table 5)

Characteristic

Nominal bus

Voltage(1)

Symbol

Min

Max

Unit

Input high voltage (all inputs except SYSLCK)(2)(3)

2.5

VIH

1.6

(L2)OVDD + 0.3

3.3

VIH

(L2)OVDD + 0.3

Input low voltage (all inputs except SYSLCK)(2)

2.5

-0.3

0.6

3.3

VIL

-0.3

0.8

SYSCLK input high voltage

2.5

KVIH

1.8

OVDD + 0.3

3.3

2.4

DD + 0.3

SYSCLK input low voltage

2.5

KVIL

-0.3

0.4

3.3

KVIL

-0.3

0.4

Input leakage current, (2)(3)

VIN = L2OVDD/OVDD

–

µA

Hi-Z (off-state) leakage current, (2)(3)(5)

VIN = L2OVDD/OVDD

TSI

–

µA

Output high voltage, I

OH = -6 mA

2.5

1.7

–

3.3

VOH

2.4

–

Output low voltage, I

OL = 6 mA

2.5

–

0.45

3.3

–

0.4

Capacitance, VIN = 0V, f = 1 MHz

(3)(4)

Cin

–

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