PC755 datasheet(27/50 Pages) ATMEL

27 / 50 page

PC755/745

2138D–HIREL–06/03

Figure 12 provides the AC test load for the PC755.

Figure 12. AC Test Load

Notes:

1. Revisions prior to Rev 2.8 (Rev E) were limited in performance and did not conform to this specification. Contact your local

Motorola sales office for more information.

2. Guaranteed by design and characterization.

3. t

SYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted low then

precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for TS, ABB or DBB is 0.5 x

SYSCLK, i.e. less than the minimum tSYSCLK period, to ensure that another master asserting TS, ABB, or DBB on the following

clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid

time is tested for precharge.The high-Z behavior is guaranteed by design.

5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in

the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the

assertion of AACK. The nominal precharge width for ARTRY is 1.0 t

SYSCLK; i.e., it should be high-Z as shown in Figure 6

before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge. The high-Z and precharge behavior is guaranteed by design.

OVDD/2

OUTPUT

Z0 = 50Ω

RL = 50Ω

Table 14. Processor Bus AC Timing Specifications

(1) at Recommended Operating Conditions

Parameter

Symbols

All Speed Grades

Unit

Min

Max

Setup Times: All Inputs

IVKH

2.5

–

Input Hold Times:

TLBISYNC, MCP, SMI

tIXKH

0.6

–

Input Hold Times: All Inputs, except

TLBISYNC, MCP, SMI

tIXKH

0.2

–

Valid Times: All Outputs

KHOV

–

4.1

Output Hold Times: All Outputs

tKHOX

–

SYSCLK to Output Enable(2)

tKHOE

0.5

–

SYSCLK to Output High Impedance (all except

ABB, ARTRY, DBB)(2)

KHOZ

–

SYSCLK to

ABB, DBB High Impedance After Precharge(2)(3)(4)

tKHABPZ

–

tSYSCLK

Maximum Delay to

ARTRY Precharge(2)(3)(5)

tKHARP

–

tSYSCLK

SYSCLK to

ARTRY High Impedance After Precharge(2)(3)(5)

KHARPZ

–

SYSCLK

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