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AD5415

Rev. 0 | Page 21 of 28

Table 11. DAC Control Bits

DAC

Function

A and B

No Operation (Power-On Default)

Load and Update

Initiate Readback

Load Input Register

Load and Update

Initiate Readback

Load Input Register

A and B

Update DAC Outputs

A and B

Load Input Registers

–

Daisy-Chain Disable

–

Clock Data to Shift Register on Rising Edge

–

Clear DAC Output to Zero

–

Clear DAC Output to Midscale

–

Control Word

–

Reserved

–

No Operation

SYNC FUNCTION

SYNC is an edge-triggered input that acts as a frame synchroni-

zation signal and chip enable. Data can be transferred into the

device only while SYNC is low. To start the serial data transfer,

SYNC should be taken low, observing the minimum SYNC

falling to SCLK falling edge setup time, t4.

DAISY-CHAIN MODE

Daisy-chain mode is the default mode at power-on. To disable

the daisy-chain function, write 1001 to the control word. In

daisy-chain mode, the internal gating on SCLK is disabled. The

SCLK is continuously applied to the input shift register when

SYNC is low. If more than 16 clock pulses are applied, the data

ripples out of the shift register and appears on the SDO line.

This data is clocked out on the rising edge of SCLK and is valid

for the next device on the falling edge (default). By connecting

this line to the DIN input on the next device in the chain, a

multidevice interface is constructed. Sixteen clock pulses are

required for each device in the system. Therefore, the total

number of clock cycles must equal 16N, where N is the total

number of devices in the chain. (See the timing diagram in

Figure 4.)

When the serial transfer to all devices is complete, SYNC should

be taken high. This prevents any further data from being

clocked into the input shift register. A burst clock containing the

exact number of clock cycles can be used and SYNC taken high

some time later. After the rising edge of SYNC, data is automati-

cally transferred from each device’s input shift register to the

addressed DAC.

When control bits are 0000, the device is in no-operation mode.

This might be useful in daisy-chain applications, where the user

does not want to change the settings of a particular DAC in the

chain. Simply write 0000 to the control bits for that DAC, and

the following data bits are ignored.

STANDALONE MODE

After power-on, writing 1001 to the control word disables daisy-

chain mode. The first falling edge of SYNC resets a counter that

counts the number of serial clocks to ensure that the correct

number of bits is shifted in and out of the serial shift registers. A

SYNC edge during the 16-bit write cycle causes the device to

abort the current write cycle.

After the falling edge of the 16th SCLK pulse, data is automati-

cally transferred from the input shift register to the DAC. In

order for another serial transfer to take place, the counter must

be reset by the falling edge of SYNC.

LDAC FUNCTION

The LDAC function allows asynchronous or synchronous

updates to the DAC output. The DAC is asynchronously

updated when this signal goes low. Alternatively, if this line is

held permanently low, an automatic or synchronous update

mode is selected, whereby the DAC is updated on the 16th clock

falling edge when the device is in standalone mode or on the

rising edge of SYNC when in daisy-chain mode.

Software LDAC Function

Load and update mode also functions as a software update

function, irrespective of the voltage level on the LDAC pin.

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