AD7760BCP datasheet(5/22 Pages) AD

5 / 22 page

Preliminary Technical Data

AD7760

Rev. PrN | Page 5 of 22

TIMING SPECIFICATIONS

Table 2.

VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25°C, CLOAD = 25pF, Full Power Mode, unless otherwise noted

Parameter

Limit at TMIN, TMAX

Unit

Description

fMCLK

12.288

MHz min

Applied Master Clock Frequency

MHz max

fICLK

12.288

MHz min

Internal Modulator Clock Derived from MCLK.

MHz max

t11

0.5 × tICLK

typ

DRDY Pulse Width

nS min

DRDY Falling Edge to CS falling Edge

nS min

RD/WR Setup Time to CS Falling Edge

nS typ

Data Access Time

tICLK

min

CS Low Pulse Width

tICLK

min

CS High Pulse Width Between Reads

nS min

RD/WR Hold Time to CS Rising Edge

nS max

Bus Relinquish Time

0.5 × tICLK

typ

DRDY High Period

t10

0.5 × tICLK

typ

DRDY Low Period

t11

nS typ

Data Access Time

t12

TBD

xS min

Data Valid Prior to DRDY Rising Edge

t13

TBD

xS min

Data Valid After DRDY Rising Edge

t14

nS max

Bus Relinquish Time

t15

tICLK

xS min

CS Low Pulse Width

t16

tICLK

xS min

CS High Period Between Address and Data

t17

nS min

Data Setup Time

t18

nS min

Data Hold Time

1 tICLK = 1/fICLK

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