AD7760BCP datasheet(12/22 Pages) AD

12 / 22 page

AD7760

Preliminary Technical Data

Rev. PrN | Page 12 of 22

THEORY OF OPERATION

The AD7760 employs a sigma-delta conversion technique to

convert the analog input into an equivalent digital word. The

modulator samples the input waveform and outputs an

equivalent digital word to the digital filter at a rate equal to I

CLK.

Due to the high over-sampling rate, which spreads the

quantization noise from 0 to f

ICLK, the noise energy contained in

the band of interest is reduced (Figure 13a). To further reduce

the quantization noise, a high order modulator is employed to

shape the noise spectrum; so that most of the noise energy is

shifted out of the band of interest (Figure 13b).

The digital filtering which follows the modulator removes the

large out-of-band quantization noise (Figure 13c) while also

reducing the data rate from f

ICLK at the input of the filter to fICLK/8

or less at the output of the filter, depending on the decimation

rate used.

Digital filtering has certain advantages over analog filtering. It

does not introduce significant noise or distortion and can be

made perfectly linear phase.

The AD7760 employs three Finite Impulse Response (FIR)

filters in series. By using different combinations of decimation

ratios and filter selection and bypassing, data can be obtained

from the AD7760 at a large range of data rates. Multi-bit data

from the modulator can be obtained at a rate of 20MHz. The

first filter receives data from the modulator at 20MHz where it

is decimated by four to output data at 5MHz. This partially

filtered data can also be output at this stage. The second filter

allows the decimation rate to be chosen from 2x to 32x or to be

BAND OF INTEREST

fICLK/2

DIGITAL FILTER CUTOFF FREQUENCY

BAND OF INTEREST

QUANTIZATION NOISE

fICLK/2

BAND OF INTEREST

fICLK/2

NOISE SHAPING

Figure 13. Sigma-Delta ADC

completely bypassed. The third filter has a fixed decimation rate

of 2x and is user programmable as well as having a default

configuration. It is described in detail in the Programmable FIR

Filter Section. This filter can also be bypassed. Table X below

shows some characteristics of the default filter. The group delay

of the filter is defined to be the delay to the centre of the

impulse response and is equal to the computation + filter delays.

The delay until valid data is available (the DVALID status bit is

set) is equal to 2x the filter delay + the computation delay.

Table 5. Configuration With Default Filter

ICLK

Frequency

Filter 1

Filter 2

Filter 3

Data State

Computation

Delay

Filter Delay

Passband

Bandwidth

Output Data

Rate (ODR)

20 MHz

Bypassed

Unfiltered

(10 MHz)

20 MHz

Bypassed

Partially Filtered

0.325

1.2µS

1.35 MHz

5 MHz

20 MHz

Bypassed

Fully Filtered

1.075

10.8µS

1 MHz

2.5 MHz

20 MHz

Bypassed

Partially Filtered

1.35

3.6µS

562.5 kHz

2.5 MHz

20 MHz

Fully Filtered

1.625

22.8µS

500 kHz

1.25 MHz

20 MHz

Bypassed

Partially Filtered

1.725

6µS

281.25 kHz

1.25 MHz

20 MHz

Fully Filtered

1.775

44.4µS

250 kHz

625 kHz

20 MHz

Bypassed

Partially Filtered

2.6

10.8µS

140.625 kHz

625 kHz

20 MHz

Fully Filtered

2.25

87.6µS

125 kHz

312.5 kHz

20 MHz

16x

Bypassed

Partially Filtered

4.175

20.4µS

70.3125 kHz

312.5 kHz

20 MHz

16x

Fully Filtered

3.1

174µS

62.5 kHz

156.25 kHz

20 MHz

32x

Bypassed

Partially Filtered

7.325

39.6µS

35.156 kHz

156.25 kHz

20 MHz

32x

Fully Filtered

4.65

346.8µS

31.25 kHz

78.125 kHz

12.288MHz

Fully Filtered

3.66

142.6µS

76.8 kHz

192 kHz

12.288MHz

16x

Fully Filtered

5.05

283.2µS

38.4 kHz

96 kHz

12.288MHz

32x

Bypassed

Partially Filtered

11.92

64.45µS

21.6 kHz

96 kHz

12.288MHz

32x

Fully Filtered

7.57

564.5µS

19.2 kHz

48 kHz

AD7760BCP Datasheet(PDF) 12 Page - Analog Devices

AD7760BCP Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL