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SL28DB200 Datasheet(PDF) 3 Page - Silicon Laboratories |
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SL28DB200 Datasheet(HTML) 3 Page - Silicon Laboratories |
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3 / 8 page ![]() SL28DB200 ......................... Document #: 38-07722 Rev *C Page 3 of 8 Output Enable Clarification OE# functionality allows for enabling and disabling individual outputs. OE1# and OE2# are Active LOW inputs. Disabling the outputs may be implemented by deasserting the OE# input pin. If the OE# pin is deasserted, the output of interest will be tri-stated. (The assertion and deassertion of this signal is absolutely asynchronous.) OE Assertion All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 SRC clock periods. In addition, SRC clocks will be driven high within 15 ns of OE# assertion to a voltage greater than 200 mV Absolute Maximum Conditions OE Deassertion The impact of deasserting OE# is that each corresponding output will transition from normal operation to tri-state in a glitch-free manner. The maximum latency from the deassertion to tri-stated outputs is between 2–6 DIF clock periods. DC Electrical Specifications Table 2. OE Functionality OE# SRC,SRC# 0 Enable 1 Tri-State Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient (Commercial Grade) Functional 0 85 °C TA Temperature, Operating Ambient (Industrial Grade) Functional -40 85 °C TJ Temperature, Junction Functional 150 °C ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 – V UL-94 Flammability Rating UL (Class) V–0 MSL Moisture Sensitivity Level 1 Parameter Description Condition Min. Max. Unit VDDA, VDD 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V VIL 3.3V Input Low Voltage VSS – 0.5 0.8 V VIH 3.3V Input High Voltage 2.0 VDD + 0.5 V IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD –5 A IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD 5 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance –- 6 pF LIN Pin Inductance – 7 nH IDD3.3V Dynamic Supply Current At max. load, Full Active, at 100MHz – 60 mA |
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