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........................ Document #: 38-07426 Rev. *C Page 5 of 11

Table 5 shows the logic for selecting the Power-down mode,

using the PwrDnB input signal. PwrDnB is active LOW

(enabled when 0). When PwrDnB is disabled, the DRCG is in

its normal mode. When PwrDnB is enabled, the DRCG is put

into a powered-off state, and the Clk and ClkB outputs are

three-stated.

Table of Frequencies and Gear Ratios

Table 6

shows

several

supported

Pclk

and

Busclk

frequencies, the corresponding A and B dividers required in

the DRCG PLL, and the corresponding M and N dividers in the

gear ratio logic. The column Ratio gives the Gear Ratio as

defined Pclk/Synclk (same as M and N). The column F@PD

gives the divided down frequency (in MHz) at the Phase

Detector, where F@PD = Pclk/M = Synclk/N.

State Transitions

The clock source has three fundamental operating states.

Figure 4 shows the state diagram with each transition labelled

A through H. Note that the clock source output may NOT be

glitch-free during state transitions.

Upon powering up the device, the device can enter any state,

depending on the settings of the control signals, PwrDnB and

StopB.

In Power-down mode, the clock source is powered down with

the control signal, PwrDnB, equal to 0. The control signals S0

and S1 must be stable before power is applied to the device,

and can only be changed in Power-down mode (PwrDnB = 0).

be grounded during the Power-down mode.

The control signals Mult0 and Mult1 can be used in two ways.

If they are changed during Power-down mode, then the

Power-down transition timings determine the settling time of

the DRCG. However, the Mult0 and Mult1 control signals can

also be changed during Normal mode. When the Mult control

signals are “hot-swapped” in this manner, the Mult transition

timings determine the settling time of the DRCG.

In Normal mode, the clock source is on, and the output is

enabled.

Table 7 lists the control signals for each state.

Figure 5 shows the timing diagrams for the various transitions

between states, and Table 8 specifies the latencies of each

state transition. Note that these transition latencies assume

the following.

Refclk input has settled and meets specification shown in the

Operating Conditions table.

The Mult0, Mult1, S0 and S1 control signals are stable.

Table 4. Bypass and Test Mode Selection

Mode

S0

S1

Bypclk

(int.)

Clk

ClkB

Normal

0

0

Gnd

PAclk

PAclkB

Output Test (OE)

0

1

–

Hi-Z

Hi-Z

Bypass

1

0

PLLclk

PLLclk

PLLclkB

Test

1

1

Refclk

Refclk

RefclkB

Table 5. Power-down Mode Selection

Mode

PwrDnB

Clk

ClkB

Normal

1

PAclk

PAclkB

Power-down

0

GND

GND

Table 6. Examples of Frequencies, Dividers, and Gear Ratios

Pclk Refclk Busclk Synclk A B M N Ratio F@PD

67

33

267

67

8 1 2 2

1.0

33

100

50

300

75

6 1 8 6

1.33

12.5

100

50

400

100

8 1 4 4

1.0

25

133

67

267

67

4 1 4 2

2.0

33

133

67

400

100

6 1 8 6

1.33

16.7

Table 7. Control Signals for Clock Source States

State

PwrDnB

StopB

Clock

Source

Output

Buffer

Power-down

0

X

OFF

Ground

Clock Stop

1

0

ON

Disabled

Normal

1

1

ON

Enabled

Test

M

N

L

K

Normal

Power-Down

Clk Stop

D

C

G

A

E

F

H

VDD Turn-On

VDD Turn-On

VDD Turn-On

VDD Turn-On

B

J

Figure 4. Clock Source State Diagram