W134

........................ Document #: 38-07426 Rev. *C Page 7 of 11

Figure 5 shows that the Clk Stop to Normal transition goes

clock output is enabled and must be glitch-free. For

50 ps of the phase before the clock output was disabled. At

this time, the clock output must also meet the voltage and

timing specifications of the Device Characteristics table. The

outputs are in a high-impedance state during the Clk Stop

mode.

E

Clk Stop

Normal

10 ns

Time from StopB until Clk/ClkB provides glitch-free

clock edges.

E

Clk Stop

Normal

ps of the phase before CLK/CLKB was disabled.

F

Normal

Clk Stop

5 ns

Time from StopB to Clk/ClkB output disabled.

LTest

Normal

3 ms

Time from when S0 or S1 is changed until CLK/CLKB

N

Normal

Test

3 ms

Time from when S0 or S1 is changed until CLK/CLKB

B,D

Normal or Clk Stop

1 ms

Time from PwrDnB to the device in Power-down.

Table 8. State Transition Latency Specifications (continued)

Transition

From

To

Transition Latency

Description

Parameter

Max.

Table 9. Distributed Loop Lock Time Specification

Parameter

Description

Min.

Max.

Unit

5ms

Table 10.Supply and Reference Current Specification

Parameter

Description

Min.

Max.

Unit

“Supply” current in Power-down state (PwrDnB 1 = 0)

–

250

µA

“Supply” current in Clk Stop state (StopB = 0)

–

65

mA

“Supply” current in Normal state (StopB = 1, PwrDnB = 1)

–

100

mA

Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)

–

50

µA

Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)

–

2

mA