PCI6620 datasheet(27/160 Pages) TI

27 / 160 page

2–11

Table 2–6. PCI System Terminals

TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

I/O

DESCRIPTION

GRST

N05

Global reset. When the global reset is asserted, the GRST signal causes the PCI6X20 device to place all output

buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is

completely in its default state. For systems that require wake-up from D3, GRST is normally asserted only

during initial boot. PRST must be asserted following initial boot so that PME context is retained when

transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST must be tied to PRST.

When the SUSPEND mode is enabled, the device is protected from the GRST, and the internal registers are

preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCLK

R01

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising

edge of PCLK.

PRST

P03

PCI bus reset. When the PCI bus reset is asserted, PRST causes the PCI6x20 device to place all output buffers

in a high-impedance state and reset some internal registers. When PRST is asserted, the device is completely

nonfunctional.

When SUSPEND is asserted, the device is protected from PRST clearing the internal registers. All outputs are

placed in a high-impedance state, but the contents of the registers are preserved.

PCI6620 Datasheet(PDF) 27 Page - Texas Instruments