ML145162 datasheet(13/24 Pages) LANSDALE

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Figure 17. TxPS/fTx and RxPS/fRx Outputs to Control Power Switches

of the Transmitter and the Receiver

POWER SWITCH FOR TRANSMITTER

VDD

UNIVERSAL DUAL PLL

RxPS/fRx

TxPS/fTx

POWER SUPPLY

POWER

AMP

Tx DIVIDER CHAIN COUNTER, PHASE DETECTOR

Tx POWER–DOWN

ENABLE FLAG

Rx DIVIDER CHAIN COUNTER, PHASE DETECTOR

Rx POWER–DOWN

ENABLE FLAG

VDD

TO CONTROL THE RECEIVER

POWER SWITCH

POWER SAVING OPERATION

This PLL has a programmable power–saving scheme. The

transmit and receive counters and the reference frequency

counter can be powered down individually by setting the TxPD

enable, RxPD enable, and Ref PD enable bits of the control

explained in Table 2 and the programming format is in Figure 8.

The output pins TxPS/fTx and RxPS/fRx output the status of

the internal power saving setting. If the bit TxPD enable is set

“high” (transmit counter is set to power–down mode), then the

TxPS/fTx pin will also output a “high” state. This TxPS/fTx

out-put can control an external power switch to switch off the

transmitter, as shown in Figure 17. This scheme can be applied

to the RxPS/fRx output to control the receiver power saving

operation as required.

LANSDALE Semiconductor, Inc.

ML145162

ML145162 Datasheet(PDF) 13 Page - LANSDALE Semiconductor Inc.