OV5116N

May 4, 2001

Version 2.1

2

SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT

1. Introduction

This section describes the features and functions of the OV5116N, a monochrome CMOS video camera integrated circuit.

* Pin 9 and Pin 24 must be used in a logical combination as per the following table:

Table 1.

Pin Descriptions

Pin #

Name

Class

Function

1, 2, 20,

23, 26

AVDD, SVDD,

DVDD, OVDD

DEVDD

Bias

Power (+5V) connections.

3

VRCHG

OA

Internal voltage reference. Connect to AGND with a 0.1uF capacitor.

4

N50

I-Ø

Set low(Ø)=standard NTSC. Set high (1)=50hz light (For use in Japan Only);

5

ABOFF

I-Ø

Auto brightness level descending function off

6

VCBRT

OA

Video DC Output Black level, leave it open in usual case

7, 21,

25, 28

SGND, DGND,

DEGND, AGND

Bias

Ground connections. Connect to supply common.

8

NTSC

I-1

Set high(1)=EIA/NTSC mode

*9

BKLT

I-Ø

Backlight mode 1

10

XTAL2

XO

Oscillator clock output or crystal output.

11

XTAL1

XI

External oscillator input or crystal input: 12.288MHz

12

FSI

I-Ø

External frame sync input. A rising edge on FSI sets the chip timing to vertical sync.

Leave open if unused.

13

OENB

I-Ø

A logic level input to enable or tri-state CVO. Logic high(1)=tri-state;low(Ø)=enabled.

14

G4X

I-Ø

A logic level input which when high places the maximum AGC gain to 4x. When low the

sensor AGC gain is 2x.

15

FAST

I-Ø

A logic level input to enable/disable AGC/AEC FAST mode. High enables, low disables,

which provides slow and smooth AGC/AEC mode.

16

BPED

I-Ø

A logic level input to disable on chip edge enhancement. High disable, low enable.

17

GAMMA

I-1

A logic level pin to select the transfer characteristic of output voltage versus light input.

Logic high for g=0.45; low for g=1.

18

FSO/MIRR

I/O

Ø/Ø

In/out pin.Frame Sync Output. Digital frame sync output pin. Positive pulse occurs during

the CVO vertical sync period. Input is a logic level input to enable mirror function.

Low(Ø)=Standard, High(1)=Mirror.

19

PCLK/G8X

I/O

Ø/Ø

Digital pixel clock output. Provides 2 functions: When high a valid pixel is present at CVO

and in sync with PCLK. Input is a logic level input to enable maximum AGC gain to 8x

(only effective when pin 14 is set to high(1))

22

CVO

Q

The composite video output signal. The output is a source follower capable of directly

driving a 1V p-p signal into a 108

*24

ATBLKT

I-Ø

Backlight mode 2

27

VREQ

OA

Internal voltage reference level. Connect to AGND with a 0.1uF capacitor.

ATB LK(Pin 24)

BLK T(Pin 9)

Mode

ØØ

Norm al Mode

Ø

1

Mode 1 - M anual B ack light

1

Ø

Mode 2 – A utom atic B ack light (Chip determ ination)

11

Future Use

Class

Default Level

I-1

digital input, w ith 100k pull up

I-Ø

digital input, w ith 100k pull dow n

I/O

digital C MOS level input and output

OA

analog C MOS reference voltage

Q

75 ohm output

XI/XO

crystal input/output

Bias

power supply bias

Ø: Low; O: Output