Document Number: 001-93639 Rev. *K

Page 4 of 31

CCG1 Datasheet

Pin Definitions

Table 1 provides the pin definition for 35-Ball WLCSP for the Cable/EMCA application. Refer to Table 23 for part numbers to package

mapping.

Table 1. Pin Definitions for 35-ball WLCSP for EMCA Cable Application

Functional Pin Name

CYPD1103-

35FNXIT

Balls

Type

Description

CC1_RX

C4

I

CC1 control

0: TX enabled

z: RX sense

CC1_TX

D7

O

Configuration Channel 1

SWD_IO

D1

I/O

SWD I/O

SWD_CLK

C1

I

SWD clock

I2C_SCL

B1

I/O

I2C_SDA

B2

I/O

XRES

B6

I

Reset

VCCD

A7

POWER

Regulated digital supply output. Connect a 1 to 1.6-µF capacitor. No

external source should be connected

VDDD

C7

POWER

Power supply for both analog and digital sections

VSSA

B7

GND

Analog ground

CC_VREF

C5

I

Data reference signal for CC lines

TX_U

B3

O

Signals for internal use only. The TX_U output signal should be

connected to the TX_M signal

TX_M

B5

I

–

TX_REF_IN

D3

I

Reference signal for internal use. Connect to TX_REF output via a

2.4K 1% resistor

TX_GND

A3

I

Connect to GND via 2K 1% resistor

TX_REF_OUT

D4

O

Reference signal generated by connecting internal current source to

two 1K external resistors

RA_DISCONNECT

E4

O

Optional control signal to remove RA after assertion of VCONN

0: RA disconnected

1: RA connected

VCONN_DET

C6

I

Local VCONN detection signal

0: VCONN is not locally applied

1: VCONN is locally applied

CC1_LPREF

A5

I

Reference signal for internal use. Connect to the output of resistor

divider from VDDD.

RA_FAR_DISCONNECT

E5

O

Optional control signal to remove RA after assertion of VCONN (NC

for 2 chip/cable)

0: RA disconnected

1: RA connected

BYPASS

D5

I

Bypass capacitor for internal analog circuits

CC1_LPRX

C3

I

Configuration channel 1 RX signal for Low Power States

GPIO

A1, A2, A4, A6,

B4, C2, D2, D6,

E1, E2, E3, E6,

E7

–

General-purpose I/Os