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CCG1 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CCG1
Description  USB Type-C Port Controller with Power Delivery
PDF  31 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CCG1 Datasheet(HTML) 1 Page - Cypress Semiconductor

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CCG1 Datasheet
USB Type-C Port Controller with Power
Delivery
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-93639 Rev. *K
Revised May 3, 2017
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support.
Applications
■ Notebooks, tablets, monitors, docking stations
■ Power adapters, USB Type-C cables
Features
32-bit MCU Subsystem
■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Integrated analog blocks
■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■ Dynamic overcurrent and overvoltage protection
Integrated digital blocks
■ Two configurable 16-bit TCPWM blocks
■ One I2C master or slave
Type-C Support
■ Integrated transceiver (BB PHY)
■ Supports up to two USB ports with PD
■ Supports routing of all protocols through an external mux
PD Support
■ Supports Provider and Consumer roles
■ Supports all power profiles
Low-Power Operation
■ 3.2 V to 5.5 V operation
■ Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
■ 40-pin QFN
■ 16-pin SOIC
■ 35-ball wafer-level CSP (WLCSP)
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).


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