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CYUSB202X

Document Number: 001-87710 Rev. *C

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SPI Interface

SD2 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 18 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Boot Options

SD2 can load boot images from various sources, selected by the

configuration of the PMODE pins. The boot options for the SD2

are as follows:

■ Boot from USB

■ Boot from I2C

■ Boot from eMMC on S0-Port

■ Boot from SPI

Reset

A reset is initiated by asserting the Reset# pin on SD2. The

specific reset sequence and timing requirements are detailed in

Figure 3 on page 15 and Table 13 on page 22. All I/Os are

tristated during a hard reset.

Clocking

SD2 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

SD2 has an on-chip oscillator circuit that uses an external

19.2 MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal option/clock frequency option.

The configuration options are shown in Table 3.

Clock inputs to SD2 must meet the phase noise and jitter require-

ments specified in Table 4.

The input clock frequency is independent of the clock/data rate

of SD2 core or any of the device interfaces. The internal PLL

applies the appropriate clock multiply option depending on the

input frequency.

32-kHz Watchdog Timer Clock Input

SD2 includes a watchdog timer that can be used to interrupt the

core, automatically wake up SD2 in Standby mode, and reset the

core. The watchdog timer runs off a 32-kHz clock, which may

optionally be supplied from an external source on a dedicated

pin of SD2.

The watchdog timer can be disabled by firmware.

Requirements for the optional 32-kHZ clock input are listed in

Table 4.

Table 2. Booting Options for SD2

PMODE[2:0][1]

Boot From

FF0

S0-Port: eMMC

On failure, USB boot enabled

FF1

USB Boot

FFF

I2C

On Failure, USB Boot is enabled

0FF

I2C only

0F1

SPI

On Failure, USB Boot is enabled

Note

1. F indicates Floating.

Table 3. Crystal/Clock Frequency Selection

FSLC[2]

FSLC[1]

FSLC[0]

Crystal/Clock

Frequency

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

Table 4. Input Clock Specifications for SD2

Parameter

Description

Specification

Units

Min

Max

Phase noise

100-Hz offset

–

–75

1-kHz offset

–

–104

10-kHz offset

–

–120

100-kHz offset

–

–128

1-MHz offset

–

–130

Maximum frequency

deviation

–150

ppm

Duty cycle

Overshoot

–

Undershoot

–

–3

Rise time/fall time

–

Table 5. 32-kHz Clock Input Requirements

Parameter

Min

Max

Units

Duty cycle

Frequency deviation

–

±200

ppm

Rise Time/fall Time

–

200

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