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CS7615 Datasheet(PDF) 23 Page - Cirrus Logic |
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CS7615 Datasheet(HTML) 23 Page - Cirrus Logic |
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23 / 36 page  CS7615 DS231PP6 23 Timing Control - HENB Registers (46h-47h) 46h: 47h: HEND Number of pixels from HREF to leading edge of HENB. Default is 1Ch. HSTART Number of pixels from HREF to trailing edge of HENB. Default is 68h. Timing Control - V1X Registers (48h-49h) 48h: 49h: V1X is a vertical register shift clock. V1R Number of pixels from HREF to leading edge of V1X. Default is 22h. V1F Number of pixels from HREF to trailing edge of V1X. Default is 36h. 76543210 HEND7 HEND6 HEND5 HEND4 HEND3 HEND2 HEND1 HEND0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HSTART7 HSTART6 HSTART5 HSTART4 HSTART3 HSTART2 HSTART1 HSTART0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V1R7 V1R6 V1R5 V1R4 V1R3 V1R2 V1R1 V1R0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V1F7 V1F6 V1F5 V1F4 V1F3 V1F2 V1F1 V1F0 r/w r/w r/w r/w r/w r/w r/w r/w |
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