S29GL01GS datasheet(28/108 Pages) CYPRESS

28 / 108 page

Document Number: 001-98285 Rev. *O

Page 28 of 108

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

The system must write the Program Resume command to exit the Program Suspend mode and continue the programming

operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after

the device has resumed programming.

Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there

must be some periods of time between resume and the next suspend command greater than or equal to tPRS in Embedded

Algorithm Controller (EAC) on page 20.

Program suspend and resume is not supported while entered in an ASO. While in program suspend entry into ASO is not supported.

5.4.3

Blank Check

The Blank Check command will confirm if the selected main flash array sector is erased. The Blank Check command does not allow

for reads to the array during the Blank Check. Reads to the array while this command is executing will return unknown data.

To initiate a Blank Check on a Sector, write 33h to address 555h in the Sector, while the EAC is in the standby state

The Blank Check command may not be written while the device is actively programming or erasing or suspended.

Use the Status Register read to confirm if the device is still busy and when complete if the sector is blank or not. Bit 7 of the Status

Register will show if the device is performing a Blank Check (similar to an erase operation). Bit 5 of the Status Register will be

cleared to 0 if the sector is erased and set to 1 if not erased.

As soon as any bit is found to not be erased, the device will halt the operation and report the results.

Once the Blank Check is completed, the EAC will return to the Standby State.

5.4.4

Erase Methods

5.4.4.1

Chip Erase

The chip erase function erases the entire main Flash Memory Array. The device does not require the system to preprogram prior to

erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all 0 data pattern prior to

electrical erase. After a successful chip erase, all locations within the device contain FFFFh. The system is not required to provide

any controls or timings during these operations. The chip erase command sequence is initiated by writing two unlock cycles,

followed by a set up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn

invokes the Embedded Erase algorithm. When WE# goes high, at the end of the 6th cycle, the RY/BY# goes low.

When the Embedded Erase algorithm is complete, the EAC returns to the standby state. Note that while the Embedded Erase

operation is in progress, the system can not read data from the device. The system can determine the status of the erase operation

by reading RY/BY#, the Status Register or using Data Polling. Refer to Status Register on page 34 for information on these status

bits. Refer to Data Polling Status on page 35 for more information.

Once the chip erase operation has begun, only a Status Read, Hardware RESET or Power cycle are valid. All other commands are

ignored. However, a Hardware Reset or Power Cycle immediately terminates the erase operation and returns to read mode after

tRPH time. If a chip erase operation is terminated, the chip erase command sequence must be reinitiated once the device has

returned to the idle state to ensure data integrity.

See Table 5.4 on page 43, Asynchronous Write Operations on page 82 and Alternate CE# Controlled Write Operations on page 88

for parameters and timing diagrams.

Sectors protected by the ASP DYB and PPB lock bits will not be erased. See ASP on page 14. If a sector is protected during chip

erase, chip erase will skip the protected sector and continue with next sector erase. The status register erase status bit and sector

lock bit are not set to 1 by a failed erase on a protected sector.

S29GL01GS Datasheet(PDF) 28 Page - Cypress Semiconductor

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