ADF4154BCP datasheet(17/20 Pages) AD

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ADF4154

Rev. 0 | Page 17 of 20

For example, in a GSM 1800 system, where a 1.8 GHz RF

frequency output (RFOUT) is required, a 13 MHz reference

frequency input (REFIN) is available and a 200 kHz channel

resolution (fRES) is required on the RF output.

kHz

200

MHz

MOD

REF

MOD

RES

From Equation 4,

FPFD = [13 MHz × (1 + 0)/1] = 13 MHz

(5)

(

)

;

138

MHz

≥

FRAC

INT

FRAC

INT

(6)

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output. For example, a GSM system with 13 MHz REFIN

would set the modulus to 65, resulting in the RF output resolu-

tion (fRES) of 200 kHz (13 MHz/65) that is necessary for GSM.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually results in an improvement in noise performance of 3 dB.

It is important to note that the PFD cannot be operated above

32 MHz due to a limitation in the speed of the Σ-Δ circuit of

the N divider.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4154 allows the

user to program the modulus over a 12-bit range. This means

that the user can set up the part in many different configura-

tions for the application, when combined with the reference

doubler and the 4-bit R counter.

For example, consider an application that requires a 1.75 GHz

RF and a 200 kHz channel step resolution. The system has a

13 MHz reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65, which would

result in the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. The 26 MHz signal is

then fed into the PFD, which programs the modulus to divide

by 130. This setup also results in 200 kHz resolution and offers

superior phase noise performance over the previous setup.

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC and

GSM 1800 standards, the programmable modulus is a huge

benefit. The PDC requires a 25 kHz channel step resolution,

whereas the GSM 1800 requires a 200 kHz channel step

resolution. A 13 MHz reference signal could be fed directly to

the PFD. The modulus would be programmed to 520 when in

PDC mode (13 MHz/520 = 25 kHz). The modulus would be

reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =

200 kHz). It is important that the PFD frequency remains con-

stant (13 MHz). By keeping the PFD constant, the user can

design a one-loop filter that can be used in both setups without

running into stability issues. The ratio of the RF frequency to

the PFD frequency affects the loop design. Keeping this

relationship constant instead of changing the modulus factor

results in a stable filter.

SPURIOUS OPTIMIZATION AND FAST-LOCK

The ADF4154 can be optimized for low spurious signals by

using the noise and spur register. However, in order to achieve

fast-lock time, a wider loop bandwidth is needed. Note that a

wider loop bandwidth can lead to notable spurious signals,

which cannot be reduced significantly by the loop filter.

Using the fast-lock feature can achieve the same fast-lock time

as the noise and spur register, but with the advantage of lower

spurious signals, since the final loop bandwidth is reduced by

a quarter.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value needs to be loaded

into the PLL to determine the time of the wide bandwidth.

When the load control bit = 1, the timer value is loaded via the

12-bit modulus value. To use fast-lock, the PLL must be written

to in the following sequence:

Load the R-divider register with DB23 = 1 and the chosen

fast-lock timer value (DB13–DB2) instead of the modulus.

Note that the duration of time the PLL remains in wide

bandwidth is equal to the fast-lock timer/FPFD.

Load the noise and spur register.

Load the control register.

Load R-divider register with DB23 = 0 and MUXOUT =

110 (DB22–DB20). All the other needed parameters,

including the modulus, also need to be loaded.

Load the N-divider register, including fast-lock = 1

(DB23), to activate fast-lock mode.

Once this procedure is completed, future frequency jumps

deploying fast-lock need to repeat only Step 5.

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