ADF4154BCP datasheet(18/20 Pages) AD

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ADF4154

Rev. 0 | Page 18 of 20

If fast-lock is not used, then use the following sequence:

Load the noise and spur register.

Load the control register.

Load the R-divider register with DB23 = 0 and other

necessary parameters.

Load the N-divider register, including fast-lock = 0

(DB23) for normal operation.

To change frequency, only Step 4 need be repeated.

FAST-LOCK: A WORKED EXAMPLE

Consider an example in which PLL has reference frequencies of

13 MHz and FPFD = 13 MHz and a required lock time of 50 µs.

Therefore, the PLL is set to wide bandwidth for 40 µs.

If the time period chosen for the wide bandwidth is 40 µs, then

Fast-lock timer value = time in wide bandwidth × FPFD

Fast-lock timer value = 40 µs × 13 MHz = 520

Therefore, 520 has to be loaded into the R-divider register in

Step 1 of the sequence described in the Fast-Lock Timer and

FAST-LOCK: LOOP FILTER TOPOLOGY

To use fast-lock mode, an extra connection from the PLL to the

loop filter is needed. The MUXOUT must reduce the damping

resistor in the loop filter to ¼ while in wide bandwidth mode.

This is required because the charge pump current is increased

by 16 while in wide bandwidth mode and stability must be

ensured. This can be done with the following two topologies:

Divide the damping resistor (R1) into two values (R1 and

R1A) of ratio 1:3 (see Figure 22).

Use an extra resistor (R1A) and connect it directly from the

MUXOUT, as shown in Figure 22. The extra resistor must

be chosen such that the parallel combination of an extra

resistor and the damping resistor (R1) is reduced to ¼ of

the original value of R1 alone (see Figure 23).

ADF4154

MUXOUT

R1A

VCO

Figure 22 Fast-lock Loop Filter Topology—Topology 1

ADF4154

MUXOUT

R1A

VCO

Figure 23. Fast-lock Loop Filter Topology—Topology 2

SPURIOUS SIGNALS

Predicting Where They Appear

As in integer-N PLLs, spurs appear at PFD frequency offsets

from the carrier. In a fractional-N PLL, spurs also appear at

frequencies equal to the RFOUT channel step resolution (fRES).

The third-order fractional interpolator engine of the ADF4154

may also introduce subfractional spurs. If the fractional deno-

minator (MOD) is divisible by 2, spurs appear at ½ fRES. If the

fractional denominator (MOD) is divisible by 3, spurs appear at

1/3 fRES. Harmonics of all spurs mentioned also appear. With the

lowest spur mode enabled, the fractional and subfractional

spurs are attenuated dramatically. The worst-case spurs appear

when the fraction is programmed to 1/MOD. For example, in a

GSM 900 MHz system with a 26 MHz PFD frequency and an

RFOUT channel step resolution (fRES) of 200 kHz, the MOD = 130.

PFD spurs appear at 26 MHz offset and fractional spurs appear

at 200 kHz offset. Since the MOD is divisible by 2, subfractional

spurs are also present at 100 kHz offset.

FILTER DESIGN—ADISIMPLL

A filter design and analysis program is available to help the user

implement the PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL software. The software designs,

simulates, and analyzes the entire PLL frequency and time

domain response. Various passive and active filter architectures

are allowed. Rev. 2 of ADIsimPLL allows analysis of the

ADF4154.

INTERFACING

The ADF4154 has a simple, SPI® compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (latch enable) is high, the 22 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 µs. This is more than adequate

for systems that have typical lock times in the hundreds of

microseconds.

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