LTC4212CMS datasheet(11/24 Pages) LINER

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LTC4212

4212f

set CTIMER = 10nF and adjust its value accordingly to suit

the specific applications.

Table 1. tTIMER vs CTIMER

CTIMER

tTIMER

0.0033

µF

2.0ms

0.0047

µF

2.9ms

0.0068

µF

4.2ms

0.0082

µF

5.1ms

0.01

µF

6.2ms

0.015

µF

9.3ms

0.022

µF

13.6ms

0.033

µF

20.4ms

0.047

µF

29.0ms

0.068

µF

42.0ms

0.082

µF

50.7ms

0.1

µF

61.8ms

0.15

µF

92.7ms

0.22

µF

136ms

0.33

µF

204ms

Power-Up Timeout Circuit

The power-up timeout circuit has two functions. During

power-up, it trips the circuit breaker if the DC/DC convert-

ers on the board do not power-up and do not enter

regulation on time. After normal power-up, it is configured

to trip the circuit breaker if any of the converters exit

regulation for longer than a programmable delay. Once the

circuit breaker is tripped, the LTC4212 is latched off and

the board is disconnected from the system supply. The ON

pin must be taken low for 120

µs to reset the circuit breaker

and then high to reconnect the board to the backplane

supply.

The power-up timeout circuit uses three pins: PGI or

power good input pin, PGT or power good timer pin and

PGF or power good filter pin. It is enabled at the end of the

second system timing cycle, provided that the FAULT pin

is high. Prior to being enabled or if FAULT is low, the PGT

and PGF pins are pulled to GND by internal N-channel

FETs, M5 and M12 respectively. When enabled, the

power-up timeout circuit starts the power good timer,

which generates a time-out period before the PGI pin is

sampled.

OPERATIO

Power Good Timer

The timer consists of COMP9, M8-M12, two 5

µA current

sources and 0.65V and 0.95V threshold voltages for

COMP9.

The PGI pin is normally connected to the RST output pin

or comparator outputs of an external supply monitor IC or

to the PGOOD pin of a DC/DC converter and drives a

comparator, COMP8 which has a threshold voltage of

1.236V and 28mV of hysterisis. The RST and PGOOD pins

are typically open drain pins and require an external pull-

up resistor. The upper end of the resistor must be con-

nected to a voltage greater than the upper threshold of the

PGI comparator (1.236V).

A capacitor, CPGT, connected from the PGT pin to ground

programs the time-out period generated by the power

good timer according to Equation 3. Table 2 shows the

power good time-out periods for a list of standard capaci-

tor values.

tTIMEOUT = 1.81Ω • CPGT

(3)

Two 5

µAcurrentsourcesareswitchedinandouttocharge

and discharge CPGT between 0.65V and 0.95V for 14

cycles.

Table 2. tTIMEOUT vs CPGT

CPGT

tTIMEOUT

3.3nF

5.97ms

4.7nF

8.51ms

6.8nF

12.3ms

8.2nF

14.8ms

0.01

µF

18.1ms

0.022

µF

39.8ms

0.033

µF

59.7ms

0.047

µF

85.1ms

0.068

µF

123ms

0.082

µF

148ms

0.1

µF

181ms

0.22

µF

136ms

0.33

µF

398ms

0.47

µF

851ms

0.68

µF

1230ms

0.82

µF

1480ms

µF

1810ms

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