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LTC4212

4212f

applications where PGI monitors the RST output of a

supply monitor like the LTC1326-2.5, the RST and there-

fore the PGI pins are held low for another 200ms until Time

Point 11 (see PGI (RST) waveform). At Time Point 12, the

power good circuit samples the PGI pin. During normal

power-up, PGI will go high before Time Point 12. The

power good circuit disables and resets the power good

timer and M12 is turned ON to pull PGT to ground. The

power good glitch filter is then enabled to monitor the

PGI pin.

Power Good Glitch Filter Sequence

The power good glitch filter sequence is also shown in

Figure 2 from Time Points 12 through 16. When the glitch

filter is enabled, M5, the internal N-channel FET that shorts

the PGF pin to GND is switched OFF whenever PGI is low.

This allows the CPGF capacitor to be charged by an internal

µA current source towards 1.236V. If the PGF pin voltage

exceeds 1.236V, the power good circuit trips the circuit

breaker to latch the part off. Tying PGF to GND disables the

glitch filter and prevents the power good from tripping the

circuit breaker after Time Point 12.

For supply monitors such as the LTC1326-2.5, the glitch

filter is less useful. The comparators in the LTC1326-2.5

that monitor the DC/DC converters have a typical propaga-

tion delay of 13

µs. If any of the monitored supplies leave

regulation for more than 13

µs, the RST signal will be

pulled low until 200ms after all the supplies re-enter

regulation. The net effect is that the LTC1326-2.5 per-

forms the glitch filtering and rejects pulses shorter than

µs. The PGOOD output of a DC/DC converter does not

have the 200ms delay of the LTC1326-2.5. Thus any low

PGOOD pulse will immediately cause CPGF to be charged

towards 1.236V (Time Points 13 and 14). CPGF values can

be selected to reject low pulses that are shorter than some

desired pulse width.

Some supply monitor ICs such as the LTC1727 provide

access to the outputs of comparators monitoring the DC/DC

converters as well as the RST output. The comparator

outputs track the converter output voltages. If the LTC4212

PGI pin is used to monitor the output of a comparator rather

than the RST output of the LTC1727, CPGF can be selected

to reject low pulses shorter than a desired pulse width.

comparator outputs of a supply monitor such as the

LTC1727 are similar to PGI (PGOOD) and PGF (PGOOD).

First Timing Cycle

When the PC board makes contact with the backplane

(Time Point 1), VCC starts to rise. While VCC < 2.23V, the

LTC4212 is in UVLO mode. The GATE pin is pulled to

ground by a 200

µA current source to shut off the external

N-channel MOSFET and the TIMER, PGT and PGF pins are

all pulled low by internal N-channel FETs M6, M5 and M12.

When VCC rises above the UVLO threshold of 2.34V (Time

Point 2), the LTC4212 waits for the ON pin to go high ( >

1.316V) and checks that the GATE is low (VGATE < 0.2V)

before initiating the first timing cycle (Time Point 3).

The first timing cycle begins with the TIMER pin up at a rate

given by Equation 1. At Time Point 4 (the timing period

programmed by CTIMER), the TIMER pin voltage equals

VTMR = 1.236V. Next the TIMER pin is pulled down by M6

to Time Point 5 where VTMR = 0.2V. At Time Point 5, the

LTC4212 checks that the FAULT pin voltage is high (VFAULT

> 1.236V) before initiating the second timing cycle. If

FAULT is forced low externally, the second timing cycle

will not start and the external N-channel FET stays OFF.

Second Timing Cycle

At the beginning of the second timing cycle (Time Point 6),

the LTC4212 FAST COMP is armed and the soft-start

circuit is enabled. The GATE pin is ramped up at a rate

given by Equation 6. If the inrush current from the backplane

supply (Equation 7) is large enough to cause the voltage

drop across the sense resistor to exceed 50mV, the soft-

start circuit activates to regulate the inrush current (Equa-

tion 5). The soft-start circuit continues to operate until

Time Point 8 when the TIMER pin voltage equals VTMR =

1.236V again. At Time Point 8, SLOW COMP is armed and

the power good circuit is enabled.

When the power good circuit is enabled, M12, the internal

N-channel FET shorting the PGT pin to ground is switched

OFF and the power good timer started. The DC/DC convert-

ers enter regulation at Time Point 10. In applications

where the PGI pin is connected to the PGOOD pin of a DC/

DC converter, PGI is pulled high shortly after the converter

enters into regulation (see PGI (PGOOD) waveform). In

OPERATIO

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