LTC4212CMS datasheet(16/24 Pages) LINER

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LTC4212

4212f

150mV, SLOW COMP trips the ECB (Time Point 10). If the

voltage across RSENSE jumps above 150mV for 500ns or

more, FAST COMP will trip the ECB.

When the ECB trips, the GATE pin is driven to GND

immediately to shut off the external N-channel FET and

disconnect the board from the backplane supply. The

FAULT pin is latched to a low state and the power good

circuit is reset. The PGT and PGF pins are shorted to

ground by internal N-channel FETs. In order to reset the

fault latch, the ON pin must be taken low for more than

120

µs (Time Points 12 to 14). After that, taking the ON pin

high (Time Point 15) starts a new power-up sequence.

Autoretry Sequence

Once the circuit breaker trips, the LTC4212 can be config-

ured to autoretry that is attempt to reconnect the backplane

supply automatically. Both FAULT and ON pins are tied

together to an external pull-up resistor to VCC (RAUTO) and

to a delay capacitor (CAUTO) as shown in Figure 5.

Figure 6 shows two autoretry sequences caused by a

persistent short. When the circuit breaker trips (Time

Point 9), an internal N-channel FET at the FAULT pin is

turned on to pull the pin low. This discharges the autoretry

capacitor, CAUTO towards ground. When the ON pin volt-

age drops below 0.455V for 10

µs (from Time Point 10),

internal logic is reset and a 200

µA current source is

connected to the GATE pin. The GATE pin is already pulled

down to ground at Time Point 9. The circuit breaker is not

reset so that the FAULT pin continues to discharge CAUTO.

After the ON pin has dropped below 0.455V for more than

120

µs (Time Point 11), the circuit breaker is reset. The

N-channel FET at the FAULT pin is switched off and the

pull-up resistor at the ON pin starts to charge CAUTO

towards the upper 1.316V threshold of the ON pin. Once

the ON pin voltage rises above 1.316V, the first timing

cycle is started. The total cooling off period for the external

N-channel FET starts at Time Point 9 when the circuit

breaker trips to Time Point 15 when the second timing

cycle is started.

OPERATIO

Electronic Circuit Breaker (ECB) Reset Sequence

The ECB reset sequence is shown in Figure 2 from Time

Points 17 through 19. At Time Point 17, the ON pin is taken

low. Ten microseconds later at Time Point 18, the internal

logic is reset and a 200

µA source is connected to the GATE

pin to pull the pin to ground. 120

µs after ON goes low

(Time Point 19), the ECB is reset. When the ON pin is taken

high at Time Point 20 a new first timing cycle is started. If

the time from Time Point 17 to Time Point 18 is less than

120

µs, the ECB is not reset and taking the ON pin high at

Time Point 20 will not start a new first timing cycle.

Power Good Timeout Fault Sequence

Figure 3 shows a power-up sequence in which the DC/DC

converters do not enter regulation on time and the power

good trips the ECB. The sequence is the same as for the

normal power-up in Figure 2 until Time Point 12 when the

power good timer times out and the PGI pin is sampled.

Since PGI is low, the power good circuit trips the ECB. The

GATE pin is pulled to ground immediately to disconnect

power to the board and the FAULT pin is latched to a

low state. The PGT and PGF pins are pulled to GND

internally by N-channel FETs. To reconnect the board to

the backplane supply, the ON pin must be taken low for at

least 120

µs to reset the ECB and then high again to start

a new first timing cycle.

Overcurrent Fault Sequence

Figure 4 shows a power-up sequence with SLOW COMP

tripping the ECB. At the beginning of the second timing

cycle (Time Point 6), the GATE pin is connected to the soft-

start circuit and FAST COMP is armed but it does not

usually trip the ECB due to the action of the soft-start

circuit on the GATE pin. The soft-start circuit regulates the

voltage across the RSENSE resistor to 50mV. At Time

Point 8, the soft-start circuit is disconnected. A 10

µA

current source pulls the GATE pin up and SLOW COMP is

armed. If a short occurs and the voltage across RSENSE

jumps above 50mV for more than 18

µs but is less than

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