LTC4258 datasheet(12/28 Pages) LINER

12 / 28 page

LTC4258

4258p

Power Enable PB (Address 19h):Power Enable Pushbutton

the Power Enable bit in the corresponding Port Status reg-

ister; the upper four bits clear the corresponding Power

Enable bit. Setting or clearing the Power Enable bits via this

shutdown, regardless of the state of detection or classifi-

cation. Note that tICUT, tSTART and disconnect events (if

enabled) will still turn off power if they occur.

The Power Enable bit cannot be set if the port has turned

off due to a tICUT or tSTART fault and the tICUT timer has not

yet counted back to zero. See Applications Information for

more information on tICUT timing.

Clearing the Power Enable bits with this register also

clears the detect and fault event bits, the Port Status

for the affected port(s).

Reset PB (Address 1Ah): Reset Pushbutton, Write Only.

Bits 0-3 reset the corresponding port by clearing the power

enable bit, the detect and fault event bits, the status regis-

ter and the detection and classification enable bits for that

port. Bit 4 returns the entire LTC4258 to the power-on

reset state; all ports are turned off, the AUTO pin is reread

and all registers are returned to their power-on defaults,

except VDDUVLO, which remains cleared. Bit 5 is reserved;

setting it has no effect. Setting bit 6 releases the Interrupt

pin if it is asserted without affecting the Event registers or

the Interrupt register. When the INT pin is released in this

way, the condition causing the LTC4258 to pull the INT pin

down must be removed before the LTC4258 will be able to

pull INT down again. This can be done by reading and

clearing the event registers or by writing a 1 into bit 7 of

this register. Setting bit 7 releases the Interrupt pin, clears

all the Event registers and clears all the bits in the Interrupt

4-5 program tSTART, the time duration before an overcur-

rent condition during port power-on is considered a tSTART

fault and the port is turned off. Note that using the tICUT and

tSTARTtimesotherthanthedefaultisnotcompliantwithIEEE

802.3af and may double or quadruple the energy dissipated

by the external MOSFETs during fault conditions. Bits 6-7

are reserved and should be read/written as 0. See Electri-

cal Characteristics for timer bit encoding. Also see the Ap-

plications Information for descriptions of tSTART, tICUT and

DC disconnect timing.

Misc Config (Address 17h): Miscellaneous Configuration,

Read/Write. Setting bit 7 enables the INT pin. If this bit is

reset, the LTC4258 will not pull down the INT pin in any

condition nor will it respond to the Alert Response Address.

This bit is set by default.

Pushbutton Registers

Note Regarding Pushbutton Registers: “Pushbutton” reg-

isters are specialized registers that trigger an event when

a 1 is written to a bit; writing a 0 to a bit will do nothing. Unlike

a standard read/write register, where setting a single bit

involves reading the register to determine its status, set-

ting the appropriate bit in software and writing back the

entire register, a pushbutton register allows a single bit to

be written without knowing or affecting the status of the

other bits in the register. Pushbutton registers are write-

only and will return 00h if read.

Det/Class Restart PB (Address 18h): Detection/Classifi-

cation Restart Pushbutton Register, Write Only. Writing a

1 to any bit in this register will start or restart a single

detection or classification cycle at the corresponding port

in Manual mode. It can also be used to set the correspond-

ing bits in the Detect/Class Enable register (address 14h)

for ports in auto or semiauto mode. The lower 4 bits affect

detection on each port while the upper 4 bits affect

classification.

LTC4258 Datasheet(PDF) 12 Page - Linear Technology

LTC4258 Datasheet(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL