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SIC437 Datasheet(PDF) 7 Page - Vishay Siliconix

Part # SIC437
Description  Synchronous Buck Regulators 28 V Input, 12 A (SiC437) and 8 A (SiC438)
PDF  25 Pages
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

SIC437 Datasheet(HTML) 7 Page - Vishay Siliconix

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SiC437, SiC438
www.vishay.com
Vishay Siliconix
S18-0030-Rev. B, 15-Jan-18
7
Document Number: 75921
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For SiC43xA, the minimum switching frequency that the
regulator will drop to is 25 kHz as the part avoids switching
frequencies in the audible range to prevent audible noise. In
this version of the part, the light load mode, is called the
ultrasonic mode.
The SiC43x has a low pin count and minimum external
components. To offer the user maximum flexibility to choose
soft start times, current limit settings, switching frequencies
and to enable or disable the light load mode, just two MODE
pins are used and a particular resistor value connected to
VDD or GND allows the user to choose various operating
modes.This is best explained by the below tables:
OUTPUT MONITORING AND PROTECTION FEATURES
Output Overcurrent Protection (OCP)
SiC43x has pulse-by-pulse overcurrent limit control. The
inductor valley current is monitored during LS FET turn-on
period through RDS(on) sensing. After a pre-defined blanking
time, the valley current is compared with internal threshold
to determine the threshold for OCP. If monitored current
is higher than threshold, HS turn-on pulse is skipped and
LS FET is kept on until the valley current returns below
OCP limit.
In the severe over-current condition, pulse-by-pulse current
limit eventually triggers output undervoltage protection
(UVP) and the device will go into hiccup mode as described
in the next section.
OCP is enabled immediately after VDD passes UVLO level.
Fig. 7 - Over-Current Protection Illustration
TABLE 1 - MODE 1 CONFIGURATION SETTINGS
OPERATION
CONNECTION
fSWITCH (kHz)
RMODE1 (k)
Skip
To AGND
300
51
500
100
750
200
1000
500
Forced CCM
To VDD
300
51
500
100
750
200
1000
500
TABLE 2 - MODE 2 CONFIGURATION SETTINGS
SOFT-START TIME
CONNECTION
ILIMIT (%)
RMODE2 (k)
4.5 ms
to AGND
30
51
54
100
78
200
100 % (18 A on SiC437)
100 % (12 A on SiC438)
500
9 ms
to VDD
30
51
54
100
78
200
100 % (18 A on SiC437)
100 % (12 A on SiC438)
500
I
load
OCP
threshold
I
inductor
GH



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