SiC437, SiC438

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Vishay Siliconix

S18-0030-Rev. B, 15-Jan-18

8

Document Number: 75921

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Output Undervoltage Protection (UVP)

25 μs, then a UVP event is recognized and both HS and LS

MOSFETs are turned off. After a period of 20 soft start

cycles, the IC attempts to re-start and goes through a soft

start cycle. If the fault condition still exists, the above cycle

will be repeated.

UVP is only active after the completion of soft-start

sequence.

Output Overvoltage Protection (OVP)

For OVP implementation, output is monitored through FB

pin. After soft start, if the voltage level at FB is above 20 %

(typ.), OVP is triggered with both the HS and LS MOSFETs

turned off. Normal operation is resumed once FB voltage

drops back to 0.672 V.

Over-Temperature Protection (OTP)

SiC43x has internal thermal monitor block that turns off both

HS and LS FETs when junction temperature is above 150 °C

(typ). A hysteresis of 35 °C is implemented, so when junction

temperature drops below 115 °C, the device restarts by

initiating soft-start sequence again.

Sequencing of Input / Output Supplies

SiC43x has no sequencing requirements on any of its

must be biased first (> 5.3 V).

Enable

The SiC43x has an enable pin to turn the part on and off.

Driving this pin high enables the device, while grounding it

turns it off.

The SiC43x enable has a weak pull down to prevent

unwanted turn on due to a floating GPIO.

There

are

no

sequencing

requirements

w.r.t

other

input / output supplies.

Pre-Bias Start-Up

In case of pre-bias startup, output is monitored through FB

pin. If the sensed voltage on FB is higher than the internal

reference ramp value, control logic prevents HS and LS FET

from switching to avoid negative output voltage spike and

excessive current sinking through LS FET.

Fig. 8 - Pre-Bias Start-Up

Power Good

pin high up to 5 V through a 10K resistor to use this signal.

Power good window is shown in the below diagram. If

voltage level on FB pin is out of this window, PG signal is

de-asserted by pulling down to GND. To prevent false

blanking time.









1.52 ms

1.57 ms

1.56 ms

1.55 ms

1.54 ms

1.53 ms

3.0 V

1.0 V

2.5 V

1.5 V

2.0 V

6.0 V

-1.5 V

3.0 V

0 V

1.5 V

V

OUT

H

DRV

L

DRV

20 to 40 clock cycles

4.5 V

VFB_Rising_Vth_OV

(typ. = 0.72 V)

VFB_Falling_Vth_OV

(typ. = 0.672 V)

VFB_Falling_Vth_UV

(typ. = 0.54 V)

VFB_Rising_Vth_UV

(typ. = 0.5775 V)

PG

Pull-high

Pull-low